[RFC PATCH 0/3] Limit pluggable display modes

Abhinav Kumar quic_abhinavk at quicinc.com
Tue Aug 30 03:33:06 UTC 2022


As reported on https://gitlab.freedesktop.org/drm/msm/-/issues/17, currently
there is no mechanism to limit the display output to the pluggable displays
and it lets users connect any monitor on any chipset based device.

This can lead to undefined behavior because lets say the display
advertises an unsupported pixel clock as its preferred resolution, then
the end-user can experience undefined behavior such as black screen,
crash or an underrun.

The capabilities of every chipset are advertised in the product
specification for both on-device displays and pluggable displays.

Documents such as [1], [2] and [3] can easily be found on the vendor's
website which advertise the max resolution support for that chipset.

Utilize this information to filter out the resolutions which have
pixel clock more than the supported limits.

This change only addresses pluggable displays because the underlying
assumption is that for the built-in displays, the display being chosen
for the product will be done so after referring to the advertised limits.

For calculating the pixel clock, the value has been taken from the CEA
speficiation if the resolution is a CEA one and from the CVT specification
for non-CEA.

This change has only been compile tested so far to get a general feedback
first and once it takes a final shape, will validate on whatever devices I have
and will appreciate help from others who have devices which I dont.

[1]: https://www.qualcomm.com/content/dam/qcomm-martech/dm-assets/documents/prod_brief_qcom_sd7c.pdf
[2]: https://www.qualcomm.com/content/dam/qcomm-martech/dm-assets/documents/prod_brief_qcom_sd7c_gen2.pdf
[3]: https://www.qualcomm.com/content/dam/qcomm-martech/dm-assets/documents/prod_brief_qcom_sd8cx_gen2.pdf

Abhinav Kumar (3):
  drm/msm/dpu: add max external pixel clock for all targets
  drm/msm: filter out modes for DSI bridge having unsupported clock
  drm/msm: filter out modes for DP/eDP bridge having unsupported clock

 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c |  8 ++++++
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h |  2 ++
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c        | 18 ++++++++----
 drivers/gpu/drm/msm/dp/dp_display.c            | 16 +++++++++--
 drivers/gpu/drm/msm/dp/dp_parser.h             |  1 -
 drivers/gpu/drm/msm/dsi/dsi.c                  |  5 ++++
 drivers/gpu/drm/msm/dsi/dsi.h                  |  6 ++--
 drivers/gpu/drm/msm/dsi/dsi_host.c             | 40 ++++++++++++++++++++++----
 drivers/gpu/drm/msm/dsi/dsi_manager.c          |  2 +-
 drivers/gpu/drm/msm/msm_drv.h                  |  9 ++++--
 10 files changed, 88 insertions(+), 19 deletions(-)

-- 
2.7.4



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