[Intel-gfx] [PATCH v6 1/1] drm/i915/pxp: Promote pxp subsystem to top-level of i915

[Teres Alexis, Alan Previn]

On Wed, 2022-11-30 at 17:42 +0000, Vivi, Rodrigo wrote:
> On Wed, 2022-11-30 at 09:32 -0800, Matt Roper wrote:
> > On Tue, Nov 29, 2022 at 06:02:45PM -0800, Alan Previn wrote:
> > > Starting with MTL, there will be two GT-tiles, a render and media
> > > tile. PXP as a service for supporting workloads with protected
> > 
> > Drive-by comment:  we've been a bit inconsistent about terminology in
> > the past, but my understanding is that we're trying to standardize on
> > "GT" for the unit that MTL has two of, and keeping the term "tile"
> > for
> > the PVC-style unit that is a combination of (GT+lmem).
> 
> I agree that this gets really confusing... but it will be hard to
> standardize this I'm afraid. Specially when we do the PVC-style-tile a
> intel_gt struct and we apparently are doing the same on MTL, no?!
> 
> So, unless the topology gets organized in the code with a standard
> name, it is hard to demand everyone to use the same one.
> 
> Besides that whenever we were discussing the pvc's one we all had
> agreed that the term "tile" was bad, hence we focused on keep the
> intel_gt ready for that.
> 
> Whenever I hear tile I think of the display buffer organization...
> and there are other "tiles" examples iirc.
> 
> 
Yeah... GPU is so complex these days, a single subssytem is like a whole SOC back in the day ... beside display tiling
formats, media's HEVC has "tiles" that is kinda like macro-blocks and who can forget render's tiled-rendering (all 3
similar but can be completely orthogonal depending on the hw config / buffer state / usage). I'm assuming this
conversation is a nit. Please correct me otherwise.