[PATCH v4 12/13] arm64: dts: qcom: sc8280xp-crd: Enable EDP

[Dmitry Baryshkov]

On 5 December 2022 20:44:32 GMT+03:00, Bjorn Andersson <quic_bjorande at quicinc.com> wrote:
>From: Bjorn Andersson <bjorn.andersson at linaro.org>
>
>The SC8280XP CRD has a EDP display on MDSS0 DP3, enable relevant nodes
>and link it together with the backlight control.
>
>Signed-off-by: Bjorn Andersson <bjorn.andersson at linaro.org>
>Signed-off-by: Bjorn Andersson <quic_bjorande at quicinc.com>
>---
>
>Changes since v3:
>- Added description of the regulator that powers the panel.
>
> arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 72 ++++++++++++++++++++++-
> 1 file changed, 71 insertions(+), 1 deletion(-)
>
>diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
>index f09810e3d956..a7d2384cbbe8 100644
>--- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
>+++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
>@@ -20,7 +20,7 @@ aliases {
> 		serial0 = &qup2_uart17;
> 	};
> 
>-	backlight {
>+	backlight: backlight {
> 		compatible = "pwm-backlight";
> 		pwms = <&pmc8280c_lpg 3 1000000>;
> 		enable-gpios = <&pmc8280_1_gpios 8 GPIO_ACTIVE_HIGH>;
>@@ -34,6 +34,22 @@ chosen {
> 		stdout-path = "serial0:115200n8";
> 	};
> 
>+	vreg_edp_3p3: regulator-edp-3p3 {
>+		compatible = "regulator-fixed";
>+
>+		regulator-name = "VREG_EDP_3P3";
>+		regulator-min-microvolt = <3300000>;
>+		regulator-max-microvolt = <3300000>;
>+
>+		gpio = <&tlmm 25 GPIO_ACTIVE_HIGH>;
>+		enable-active-high;
>+
>+		pinctrl-names = "default";
>+		pinctrl-0 = <&edp_reg_en>;
>+
>+		regulator-boot-on;
>+	};
>+
> 	vreg_edp_bl: regulator-edp-bl {
> 		compatible = "regulator-fixed";
> 
>@@ -230,6 +246,54 @@ vreg_l9d: ldo9 {
> 	};
> };
> 
>+&dispcc0 {
>+	status = "okay";
>+};
>+
>+&mdss0 {
>+	status = "okay";
>+};
>+
>+&mdss0_dp3 {
>+	compatible = "qcom,sc8280xp-edp";
>+	status = "okay";
>+
>+	data-lanes = <0 1 2 3>;
>+
>+	aux-bus {
>+		panel {
>+			compatible = "edp-panel";
>+			power-supply = <&vreg_edp_3p3>;
>+
>+			backlight = <&backlight>;
>+
>+			ports {
>+				port {
>+					edp_panel_in: endpoint {
>+						remote-endpoint = <&mdss0_dp3_out>;
>+					};
>+				};
>+			};
>+		};
>+	};
>+
>+	ports {
>+		port at 1 {
>+			reg = <1>;

You already have reg assignment in the SoC dtsi.

>+			mdss0_dp3_out: endpoint {
>+				remote-endpoint = <&edp_panel_in>;
>+			};
>+		};
>+	};
>+};
>+
>+&mdss0_dp3_phy {
>+	status = "okay";
>+
>+	vdda-phy-supply = <&vreg_l6b>;
>+	vdda-pll-supply = <&vreg_l3b>;
>+};
>+
> &pcie2a {
> 	perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
> 	wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
>@@ -496,6 +560,12 @@ hastings_reg_en: hastings-reg-en-state {
> &tlmm {
> 	gpio-reserved-ranges = <74 6>, <83 4>, <125 2>, <128 2>, <154 7>;
> 
>+	edp_reg_en: edp-reg-en-state {
>+		pins = "gpio25";
>+		function = "gpio";
>+		output-enable;
>+	};
>+
> 	kybd_default: kybd-default-state {
> 		disable-pins {
> 			pins = "gpio102";

-- 
With best wishes
Dmitry