[PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Marek Vasut]

On 12/16/22 13:41, Alexander Stein wrote:
> Hi,

Hi,

> thanks for the new update.
> 
> Am Mittwoch, 14. Dezember 2022, 13:58:49 CET schrieb Jagan Teki:
>> This series supports common bridge support for Samsung MIPI DSIM
>> which is used in Exynos and i.MX8MM SoC's.
>>
>> The final bridge supports both the Exynos and i.MX8M Mini/Nano/Plus.
>>
>> Patch 0001 - 0004: adding devm_drm_of_dsi_get_bridge
>>
>> Patch 0005 - 0006: optional PHY, PMS_P offset
>>
>> Patch 0007       : introduce hw_type
>>
>> Patch 0008	 : fixing host init
>>
>> Patch 0009	 : atomic_check
>>
>> Patch 0010	 : input_bus_flags
>>
>> Patch 0011	 : atomic_get_input_bus_fmts
>>
>> Patch 0012 - 0013: component vs bridge
>>
>> Patch 0014	 : DSIM bridge
>>
>> Patch 0015 - 0016: i.MX8M Mini/Nano
>>
>> Patch 0017 - 0018: i.MX8M Plus
> 
> Tested using LVDS bridges and works on:
> * imx8mp-tqma8mpql-mba8mpxl (i.MX8M Plus)
> * imx8mm-tqma8mqml-mba8mx (i.MX8M Mini)
> * imx8mn-tqma8mqnl-mba8mx (i.MX8M Nano)
> 
> But I noticed that tqma8mqml and tqma8mqnl only have a stable output if I
> specify 'data-lanes = <0 1 2>' (not <0 1 2 3>!) on the DSI-LVDS-Bridge (TI
> SN65DSI83) input endpoint, e.g.
> 
> dsi_lvds_bridge: bridge at 2d {
> 	compatible = "ti,sn65dsi83";
> 	reg = <0x2d>;
> 	enable-gpios = <&gpio_delays 0 130000 0>;
> 	vcc-supply = <&reg_sn65dsi83_1v8>;
> 	status = "okay";
> 	ports {
> 		#address-cells = <1>;
> 		#size-cells = <0>;
> 		port at 0 {
> 			reg = <0>;
> 			lvds_bridge_in: endpoint {
> 				data-lanes = <0 1 2>;
> 				remote-endpoint = <&mipi_dsi_out>;
> 			};
> 		};
> 		port at 2 {
> 			reg = <2>;
> 			lvds_bridge_out: endpoint {
> 				remote-endpoint = <&panel_in_lvds0>;
> 			};
> 		};
> 	};
> };
> 
> I have no idea if this is on the DSIM side or the DSI-LVDS bridge side.
> Register 0xe5 on sn65dsi83 shows that CHA_LPP_ERR and CHA_SOT_BIT_ERR error
> bits are set, indicating there are low level protocol and SoT leader sequence
> bit errors. I can't find any significant difference in sn65dsi83 driver
> compared to downstream-kernel, so I would assume something in DSIM driver is
> different.

Make sure the HS clock rate expected by the DSI83 bridge chip and the 
one generated by the DSIM bridge from PMS PLL match. There is currently 
no negotiation of this frequency and both sides divine it on their own.

See sn65dsi83_get_dsi_range() and samsung_dsim_set_pll().