[PATCH] drm/msm/dpu: Use indexed array initializer to prevent mismatches

[Dmitry Baryshkov]

On 26/02/2022 22:46, Marijn Suijten wrote:
> While there's a comment pointing from dpu_intr_set to dpu_hw_intr_reg
> and vice-versa, an array initializer using indices makes it so that the
> indices between the enum and array cannot possibly get out of sync even
> if they're accidentially ordered wrongly.  It is still useful to keep
> the comment to be made aware where the register offset mapping resides
> while looking at dpu_hw_intr_reg.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov at linaro.org>

> 
> Signed-off-by: Marijn Suijten <marijn.suijten at somainline.org>
> ---
>   .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 34 +++++++++----------
>   1 file changed, 17 insertions(+), 17 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> index c515b7cf922c..c61b5b283f08 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> @@ -54,87 +54,87 @@ struct dpu_intr_reg {
>    * When making changes be sure to sync with dpu_hw_intr_reg
>    */
>   static const struct dpu_intr_reg dpu_intr_set[] = {
> -	{
> +	[MDP_SSPP_TOP0_INTR] = {
>   		MDP_SSPP_TOP0_OFF+INTR_CLEAR,
>   		MDP_SSPP_TOP0_OFF+INTR_EN,
>   		MDP_SSPP_TOP0_OFF+INTR_STATUS
>   	},
> -	{
> +	[MDP_SSPP_TOP0_INTR2] = {
>   		MDP_SSPP_TOP0_OFF+INTR2_CLEAR,
>   		MDP_SSPP_TOP0_OFF+INTR2_EN,
>   		MDP_SSPP_TOP0_OFF+INTR2_STATUS
>   	},
> -	{
> +	[MDP_SSPP_TOP0_HIST_INTR] = {
>   		MDP_SSPP_TOP0_OFF+HIST_INTR_CLEAR,
>   		MDP_SSPP_TOP0_OFF+HIST_INTR_EN,
>   		MDP_SSPP_TOP0_OFF+HIST_INTR_STATUS
>   	},
> -	{
> +	[MDP_INTF0_INTR] = {
>   		MDP_INTF_0_OFF+INTF_INTR_CLEAR,
>   		MDP_INTF_0_OFF+INTF_INTR_EN,
>   		MDP_INTF_0_OFF+INTF_INTR_STATUS
>   	},
> -	{
> +	[MDP_INTF1_INTR] = {
>   		MDP_INTF_1_OFF+INTF_INTR_CLEAR,
>   		MDP_INTF_1_OFF+INTF_INTR_EN,
>   		MDP_INTF_1_OFF+INTF_INTR_STATUS
>   	},
> -	{
> +	[MDP_INTF2_INTR] = {
>   		MDP_INTF_2_OFF+INTF_INTR_CLEAR,
>   		MDP_INTF_2_OFF+INTF_INTR_EN,
>   		MDP_INTF_2_OFF+INTF_INTR_STATUS
>   	},
> -	{
> +	[MDP_INTF3_INTR] = {
>   		MDP_INTF_3_OFF+INTF_INTR_CLEAR,
>   		MDP_INTF_3_OFF+INTF_INTR_EN,
>   		MDP_INTF_3_OFF+INTF_INTR_STATUS
>   	},
> -	{
> +	[MDP_INTF4_INTR] = {
>   		MDP_INTF_4_OFF+INTF_INTR_CLEAR,
>   		MDP_INTF_4_OFF+INTF_INTR_EN,
>   		MDP_INTF_4_OFF+INTF_INTR_STATUS
>   	},
> -	{
> +	[MDP_INTF5_INTR] = {
>   		MDP_INTF_5_OFF+INTF_INTR_CLEAR,
>   		MDP_INTF_5_OFF+INTF_INTR_EN,
>   		MDP_INTF_5_OFF+INTF_INTR_STATUS
>   	},
> -	{
> +	[MDP_AD4_0_INTR] = {
>   		MDP_AD4_0_OFF + MDP_AD4_INTR_CLEAR_OFF,
>   		MDP_AD4_0_OFF + MDP_AD4_INTR_EN_OFF,
>   		MDP_AD4_0_OFF + MDP_AD4_INTR_STATUS_OFF,
>   	},
> -	{
> +	[MDP_AD4_1_INTR] = {
>   		MDP_AD4_1_OFF + MDP_AD4_INTR_CLEAR_OFF,
>   		MDP_AD4_1_OFF + MDP_AD4_INTR_EN_OFF,
>   		MDP_AD4_1_OFF + MDP_AD4_INTR_STATUS_OFF,
>   	},
> -	{
> +	[MDP_INTF0_7xxx_INTR] = {
>   		MDP_INTF_0_OFF_REV_7xxx+INTF_INTR_CLEAR,
>   		MDP_INTF_0_OFF_REV_7xxx+INTF_INTR_EN,
>   		MDP_INTF_0_OFF_REV_7xxx+INTF_INTR_STATUS
>   	},
> -	{
> +	[MDP_INTF1_7xxx_INTR] = {
>   		MDP_INTF_1_OFF_REV_7xxx+INTF_INTR_CLEAR,
>   		MDP_INTF_1_OFF_REV_7xxx+INTF_INTR_EN,
>   		MDP_INTF_1_OFF_REV_7xxx+INTF_INTR_STATUS
>   	},
> -	{
> +	[MDP_INTF2_7xxx_INTR] = {
>   		MDP_INTF_2_OFF_REV_7xxx+INTF_INTR_CLEAR,
>   		MDP_INTF_2_OFF_REV_7xxx+INTF_INTR_EN,
>   		MDP_INTF_2_OFF_REV_7xxx+INTF_INTR_STATUS
>   	},
> -	{
> +	[MDP_INTF3_7xxx_INTR] = {
>   		MDP_INTF_3_OFF_REV_7xxx+INTF_INTR_CLEAR,
>   		MDP_INTF_3_OFF_REV_7xxx+INTF_INTR_EN,
>   		MDP_INTF_3_OFF_REV_7xxx+INTF_INTR_STATUS
>   	},
> -	{
> +	[MDP_INTF4_7xxx_INTR] = {
>   		MDP_INTF_4_OFF_REV_7xxx+INTF_INTR_CLEAR,
>   		MDP_INTF_4_OFF_REV_7xxx+INTF_INTR_EN,
>   		MDP_INTF_4_OFF_REV_7xxx+INTF_INTR_STATUS
>   	},
> -	{
> +	[MDP_INTF5_7xxx_INTR] = {
>   		MDP_INTF_5_OFF_REV_7xxx+INTF_INTR_CLEAR,
>   		MDP_INTF_5_OFF_REV_7xxx+INTF_INTR_EN,
>   		MDP_INTF_5_OFF_REV_7xxx+INTF_INTR_STATUS
> 
> base-commit: 06aeb1495c39c86ccfaf1adadc1d2200179f16eb


-- 
With best wishes
Dmitry