[PATCH AUTOSEL 5.15 123/188] drm/tegra: dc: rgb: Allow changing PLLD rate on Tegra30+

[Sasha Levin]

On Tue, Jan 18, 2022 at 12:39:43PM +0300, Dmitry Osipenko wrote:
>18.01.2022 12:37, Dmitry Osipenko пишет:
>> 18.01.2022 05:30, Sasha Levin пишет:
>>> From: Dmitry Osipenko <digetx at gmail.com>
>>>
>>> [ Upstream commit 0c921b6d4ba06bc899fd84d3ce1c1afd3d00bc1c ]
>>>
>>> Asus Transformer TF700T is a Tegra30 tablet device which uses RGB->DSI
>>> bridge that requires a precise clock rate in order to operate properly.
>>> Tegra30 has a dedicated PLL for each display controller, hence the PLL
>>> rate can be changed freely. Allow PLL rate changes on Tegra30+ for RGB
>>> output. Configure the clock rate before display controller is enabled
>>> since DC itself may be running off this PLL and it's not okay to change
>>> the rate of the active PLL that doesn't support dynamic frequency
>>> switching since hardware will hang.
>>>
>>> Tested-by: Maxim Schwalm <maxim.schwalm at gmail.com> #TF700T
>>> Signed-off-by: Dmitry Osipenko <digetx at gmail.com>
>>> Signed-off-by: Thierry Reding <treding at nvidia.com>
>>> Signed-off-by: Sasha Levin <sashal at kernel.org>
>>> ---
>>>  drivers/gpu/drm/tegra/dc.c  | 27 ++++++++++++--------
>>>  drivers/gpu/drm/tegra/dc.h  |  1 +
>>>  drivers/gpu/drm/tegra/rgb.c | 49 +++++++++++++++++++++++++++++++++++--
>>>  3 files changed, 65 insertions(+), 12 deletions(-)
>>
>> Hi,
>>
>> This patch shouldn't be ported to any stable kernel because h/w that
>> needs this patch was just merged to the 5.17.
>
>* support of h/w that needs..

I'll drop it, thanks!

-- 
Thanks,
Sasha