[PATCH 07/12] drm/i915/guc: Route semaphores to GuC for Gen12+

[Ceraolo Spurio, Daniele]

On 7/12/2022 4:31 PM, John.C.Harrison at Intel.com wrote:
> From: Michał Winiarski <michal.winiarski at intel.com>
>
> Since we're going to use semaphores in selftests (and eventually in
> regular GuC submission), let's route semaphores to GuC.

I'd specify that this interrupt is only relevant for semaphores that 
context switch out when their condition is not satisfied, which is not 
something we currently allow (but we do plan to as you mentioned). Also, 
the routing only happens when in GuC submission mode.

Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com>

Daniele

>
> Signed-off-by: Michał Winiarski <michal.winiarski at intel.com>
> ---
>   drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h        |  4 ++++
>   drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 14 ++++++++++++++
>   2 files changed, 18 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
> index 8dc063f087eb1..a7092f711e9cd 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
> @@ -102,6 +102,10 @@
>   #define   GUC_SEND_TRIGGER		  (1<<0)
>   #define GEN11_GUC_HOST_INTERRUPT	_MMIO(0x1901f0)
>   
> +#define GEN12_GUC_SEM_INTR_ENABLES	_MMIO(0xc71c)
> +#define   GUC_SEM_INTR_ROUTE_TO_GUC	BIT(31)
> +#define   GUC_SEM_INTR_ENABLE_ALL	(0xff)
> +
>   #define GUC_NUM_DOORBELLS		256
>   
>   /* format of the HW-monitored doorbell cacheline */
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index 40f726c61e951..7537459080278 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -3953,13 +3953,27 @@ int intel_guc_submission_setup(struct intel_engine_cs *engine)
>   
>   void intel_guc_submission_enable(struct intel_guc *guc)
>   {
> +	struct intel_gt *gt = guc_to_gt(guc);
> +
> +	/* Enable and route to GuC */
> +	if (GRAPHICS_VER(gt->i915) >= 12)
> +		intel_uncore_write(gt->uncore, GEN12_GUC_SEM_INTR_ENABLES,
> +				   GUC_SEM_INTR_ROUTE_TO_GUC |
> +				   GUC_SEM_INTR_ENABLE_ALL);
> +
>   	guc_init_lrc_mapping(guc);
>   	guc_init_engine_stats(guc);
>   }
>   
>   void intel_guc_submission_disable(struct intel_guc *guc)
>   {
> +	struct intel_gt *gt = guc_to_gt(guc);
> +
>   	/* Note: By the time we're here, GuC may have already been reset */
> +
> +	/* Disable and route to host */
> +	if (GRAPHICS_VER(gt->i915) >= 12)
> +		intel_uncore_write(gt->uncore, GEN12_GUC_SEM_INTR_ENABLES, 0x0);
>   }
>   
>   static bool __guc_submission_supported(struct intel_guc *guc)