[PATCH] drm/msm/dpu: populate wb or intf before reset_intf_cfg
Jessica Zhang
quic_jesszhan at quicinc.com
Wed Jul 20 15:53:13 UTC 2022
On 7/15/2022 12:14 PM, Abhinav Kumar wrote:
> dpu_encoder_helper_phys_cleanup() was not populating neither
> wb or intf to the intf_cfg before calling the reset_intf_cfg().
>
> This causes the reset of the active bits of wb/intf to be
> skipped which is incorrect.
>
> Fix this by populating the relevant wb or intf indices correctly.
>
> Fixes: ae4d721ce100 ("drm/msm/dpu: add an API to reset the encoder related hw blocks")
> Signed-off-by: Abhinav Kumar <quic_abhinavk at quicinc.com>
Reviewed-by: Jessica Zhang <quic_jesszhan at quicinc.com>
Tested-by: Jessica Zhang <quic_jesszhan at quicinc.com> # Trogdor (SC8170)
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> index c682d4e02d1b..52a626117f70 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> @@ -2061,6 +2061,12 @@ void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc)
>
> intf_cfg.stream_sel = 0; /* Don't care value for video mode */
> intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
> +
> + if (phys_enc->hw_intf)
> + intf_cfg.intf = phys_enc->hw_intf->idx;
> + if (phys_enc->hw_wb)
> + intf_cfg.wb = phys_enc->hw_wb->idx;
> +
> if (phys_enc->hw_pp->merge_3d)
> intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->idx;
>
> --
> 2.7.4
>
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