[PATCH v2 04/21] drm/i915/gt: Only invalidate TLBs exposed to user manipulation

[Andi Shyti]

Hi Mauro,

On Thu, Jul 14, 2022 at 01:06:09PM +0100, Mauro Carvalho Chehab wrote:
> From: Chris Wilson <chris.p.wilson at intel.com>
> 
> Don't flush TLBs when the buffer is only used in the GGTT under full
> control of the kernel, as there's no risk of concurrent access
> and stale access from prefetch.
> 
> We only need to invalidate the TLB if they are accessible by the user.
> That helps to reduce the performance regression introduced by TLB
> invalidate logic.
> 
> Cc: stable at vger.kernel.org
> Fixes: 7938d61591d3 ("drm/i915: Flush TLBs before releasing backing store")
> Signed-off-by: Chris Wilson <chris.p.wilson at intel.com>
> Cc: Fei Yang <fei.yang at intel.com>
> Cc: Andi Shyti <andi.shyti at linux.intel.com>
> Acked-by: Thomas Hellström <thomas.hellstrom at linux.intel.com>
> Signed-off-by: Mauro Carvalho Chehab <mchehab at kernel.org>

Please, once you have sorted out Tvrtko's question you can add:

Reviewed-by: Andi Shyti <andi.shyti at linux.intel.com>

Thanks,
Andi