[Intel-gfx] [PATCH 09/10] drm/i915: turn on small BAR support

[Matthew Auld]

On 17/06/2022 13:33, Thomas Hellström wrote:
> 
> On 5/25/22 20:43, Matthew Auld wrote:
>> With the uAPI in place we should now have enough in place to ensure a
>> working system on small BAR configurations.
>>
>> Signed-off-by: Matthew Auld <matthew.auld at intel.com>
>> Cc: Thomas Hellström <thomas.hellstrom at linux.intel.com>
>> Cc: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
>> Cc: Tvrtko Ursulin <tvrtko.ursulin at linux.intel.com>
>> Cc: Jon Bloomfield <jon.bloomfield at intel.com>
>> Cc: Daniel Vetter <daniel.vetter at ffwll.ch>
>> Cc: Jordan Justen <jordan.l.justen at intel.com>
>> Cc: Kenneth Graunke <kenneth at whitecape.org>
>> Cc: Akeem G Abodunrin <akeem.g.abodunrin at intel.com>
>> ---
>>   drivers/gpu/drm/i915/gt/intel_region_lmem.c | 10 ++++------
>>   1 file changed, 4 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c 
>> b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
>> index e9c12e0d6f59..6c6f8cbd7321 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
>> @@ -111,12 +111,6 @@ static struct intel_memory_region 
>> *setup_lmem(struct intel_gt *gt)
>>           flat_ccs_base = intel_gt_read_register(gt, 
>> XEHPSDV_FLAT_CCS_BASE_ADDR);
>>           flat_ccs_base = (flat_ccs_base >> XEHPSDV_CCS_BASE_SHIFT) * 
>> SZ_64K;
>> -        /* FIXME: Remove this when we have small-bar enabled */
>> -        if (pci_resource_len(pdev, 2) < lmem_size) {
>> -            drm_err(&i915->drm, "System requires small-BAR support, 
>> which is currently unsupported on this kernel\n");
>> -            return ERR_PTR(-EINVAL);
>> -        }
>> -
>>           if (GEM_WARN_ON(lmem_size < flat_ccs_base))
>>               return ERR_PTR(-EIO);
>> @@ -169,6 +163,10 @@ static struct intel_memory_region 
>> *setup_lmem(struct intel_gt *gt)
>>       drm_info(&i915->drm, "Local memory available: %pa\n",
>>            &lmem_size);
>> +    if (io_size < lmem_size)
>> +        drm_info(&i915->drm, "Using a reduced BAR size of %lluMiB. 
>> Consider enabling the full BAR size if available in the BIOS.\n",
>> +             (u64)io_size >> 20);
>> +
> 
> Hmm. I wonder what BIOS uis typically call the mappable portion of VRAM. 
> I'll se if I can check that on my DG1 system. Might be that an average 
> user misinterprets "full BAR".

"PCI Subsystem settings" -> "Above 4G memory [enabled/disabled]"

Sample size of one though.

Maybe s/full BAR size/full memory size/ ?

> 
> /Thomas
> 
> 
> 
>>       return mem;
>>   err_region_put: