[Intel-gfx] [PATCH] drm/i915/gtt: reduce overzealous alignment constraints for GGTT

[Das, Nirmoy]

|Acked-by: Nirmoy Das <nirmoy.das at intel.com>|

On 03/03/2022 11:02, Matthew Auld wrote:
> Currently this will enforce both 2M alignment and padding for any LMEM
> pages inserted into the GGTT. However, this was only meant to be applied
> to the compact-pt layout with the ppGTT. For the GGTT we can reduce the
> alignment and padding to 64K.
>
> Bspec: 45015
> Fixes: 87bd701ee268 ("drm/i915: enforce min GTT alignment for discrete cards")
> Signed-off-by: Matthew Auld<matthew.auld at intel.com>
> Cc: Thomas Hellström<thomas.hellstrom at linux.intel.com>
> Cc: Robert Beckett<bob.beckett at collabora.com>
> Cc: Ramalingam C<ramalingam.c at intel.com>
> ---
>   drivers/gpu/drm/i915/gt/intel_gtt.c | 3 ++-
>   1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
> index 4bcdfcab3642..a5f5b2dda332 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
> @@ -234,7 +234,8 @@ void i915_address_space_init(struct i915_address_space *vm, int subclass)
>   	memset64(vm->min_alignment, I915_GTT_MIN_ALIGNMENT,
>   		 ARRAY_SIZE(vm->min_alignment));
>   
> -	if (HAS_64K_PAGES(vm->i915) && NEEDS_COMPACT_PT(vm->i915)) {
> +	if (HAS_64K_PAGES(vm->i915) && NEEDS_COMPACT_PT(vm->i915) &&
> +	    subclass == VM_CLASS_PPGTT) {
>   		vm->min_alignment[INTEL_MEMORY_LOCAL] = I915_GTT_PAGE_SIZE_2M;
>   		vm->min_alignment[INTEL_MEMORY_STOLEN_LOCAL] = I915_GTT_PAGE_SIZE_2M;
>   	} else if (HAS_64K_PAGES(vm->i915)) {
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