[PATCH v2] drm/mgag200: Fix PLL setup for g200wb and g200ew

[Thomas Zimmermann]

Hi

Am 08.03.22 um 18:43 schrieb Jocelyn Falempe:
> commit f86c3ed55920 ("drm/mgag200: Split PLL setup into compute and
>   update functions") introduced a regression for g200wb and g200ew.
> The PLLs are not set up properly, and VGA screen stays
> black, or displays "out of range" message.
> 
> MGA1064_WB_PIX_PLLC_N/M/P was mistakenly replaced with
> MGA1064_PIX_PLLC_N/M/P which have different addresses.
> 
> Patch tested on a Dell T310 with g200wb
> 
> Fixes: f86c3ed55920 ("drm/mgag200: Split PLL setup into compute and update functions")
> Cc: stable at vger.kernel.org
> Signed-off-by: Jocelyn Falempe <jfalempe at redhat.com>

Thank you so much. I've added the patch to drm-misc-fixes. One small 
nit: next time, please include a little change log that says what each 
version of the patch changes; even if it's only the style of the commit 
message.

Best regards
Thomas

> ---
>   drivers/gpu/drm/mgag200/mgag200_pll.c | 6 +++---
>   1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/mgag200/mgag200_pll.c b/drivers/gpu/drm/mgag200/mgag200_pll.c
> index e9ae22b4f813..52be08b744ad 100644
> --- a/drivers/gpu/drm/mgag200/mgag200_pll.c
> +++ b/drivers/gpu/drm/mgag200/mgag200_pll.c
> @@ -404,9 +404,9 @@ mgag200_pixpll_update_g200wb(struct mgag200_pll *pixpll, const struct mgag200_pl
>   		udelay(50);
>   
>   		/* program pixel pll register */
> -		WREG_DAC(MGA1064_PIX_PLLC_N, xpixpllcn);
> -		WREG_DAC(MGA1064_PIX_PLLC_M, xpixpllcm);
> -		WREG_DAC(MGA1064_PIX_PLLC_P, xpixpllcp);
> +		WREG_DAC(MGA1064_WB_PIX_PLLC_N, xpixpllcn);
> +		WREG_DAC(MGA1064_WB_PIX_PLLC_M, xpixpllcm);
> +		WREG_DAC(MGA1064_WB_PIX_PLLC_P, xpixpllcp);
>   
>   		udelay(50);
>   

-- 
Thomas Zimmermann
Graphics Driver Developer
SUSE Software Solutions Germany GmbH
Maxfeldstr. 5, 90409 Nürnberg, Germany
(HRB 36809, AG Nürnberg)
Geschäftsführer: Ivo Totev
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