[PATCH] drm/i915: avoid concurrent writes to aux_inv

[Yang, Fei]

>>> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>>> b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>>> index e1470bb60f34..7e8552414275 100644
>>> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>>> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>>> @@ -1258,6 +1258,34 @@ static bool completed(const struct i915_request 
>>> *rq)
>>>  	return __i915_request_is_complete(rq);  }
>>>  
>>> +static i915_reg_t aux_inv_reg(const struct intel_engine_cs *engine) {
>>> +	static const i915_reg_t vd[] = {
>>> +		GEN12_VD0_AUX_NV,
>>> +		GEN12_VD1_AUX_NV,
>>> +		GEN12_VD2_AUX_NV,
>>> +		GEN12_VD3_AUX_NV,
>>> +	};
>>> +
>>> +	static const i915_reg_t ve[] = {
>>> +		GEN12_VE0_AUX_NV,
>>> +		GEN12_VE1_AUX_NV,
>>> +	};
>>> +
>>> +	if (engine->class == VIDEO_DECODE_CLASS) {
>>> +		GEM_BUG_ON(engine->instance >= ARRAY_SIZE(vd));
>>> +		return vd[engine->instance];
>>> +	}
>>> +
>>> +	if (engine->class == VIDEO_ENHANCEMENT_CLASS) {
>>> +		GEM_BUG_ON(engine->instance >= ARRAY_SIZE(ve));
>>> +		return ve[engine->instance];
>>> +	}
>>> +
>>> +	GEM_BUG_ON("unknown aux_inv reg\n");
>>> +	return INVALID_MMIO_REG;
>>> +}
>>> +
>>>  static void execlists_dequeue(struct intel_engine_cs *engine)
>> 
>> So in the previous implementation, this "worked" for both execlists and guc submission. But how will this work now for GuC based submission?
>> This flow and the address of the engine is owned by the GuC.
>>
>> If we are going to say this is an execlist only requirement (e.g.
>> platforms using GuC submission don't need this workaround), you should add an if (!using guc submission) in the sequence you added to the various emit_flush() routines above.
>
> Good point.
> I didn't consider GuC submission because Chrome doesn't enable GuC for TGL. But it is true that the implementation will have problem with GuC submission.
> I'm not sure if it's possible for i915 to know which engine will eventually carry out the request because it might be scheduled by GuC. I will need to investigate.

I think the same can be done in intel_guc_submission.c after __i915_request_submit(rq) calls.

>> Thanks,
>> Stuart