[PATCH v13 3/6] dt-bindings: display: Add Loongson display controller
Jiaxun Yang
jiaxun.yang at flygoat.com
Wed Mar 30 09:01:51 UTC 2022
在2022年3月30日三月 上午4:46，Sui Jingfeng写道：
> On 2022/3/29 21:27, Rob Herring wrote:
>> On Sun, Mar 27, 2022 at 9:29 PM Sui Jingfeng <15330273260 at 189.cn> wrote:
>>> Add DT bindings and simple usages for Loongson display controller
>>> found in LS7A1000 bridge chip and LS2k1000 SoC.
>>>
>>> Signed-off-by: Sui Jingfeng <15330273260 at 189.cn>
>>> ---
>>> .../loongson/loongson,display-controller.yaml | 321 ++++++++++++++++++
>>> 1 file changed, 321 insertions(+)
>>> create mode 100644 Documentation/devicetree/bindings/display/loongson/loongson,display-controller.yaml
>>>
>>> diff --git a/Documentation/devicetree/bindings/display/loongson/loongson,display-controller.yaml b/Documentation/devicetree/bindings/display/loongson/loongson,display-controller.yaml
>>> new file mode 100644
>>> index 000000000000..34060ed55a25
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/display/loongson/loongson,display-controller.yaml
>>> @@ -0,0 +1,321 @@
>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>> +%YAML 1.2
>>> +---
>>> +$id: http://devicetree.org/schemas/display/loongson/loongson,display-controller.yaml#
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: Loongson LS7A1000/LS2K1000/LS2K0500 Display Controller Device Tree Bindings
>>> +
>>> +maintainers:
>>> + - Sui Jingfeng <suijingfeng at loongson.cn>
>>> +
>>> +description: |+
>>> +
>>> + Loongson display controllers are simple which require scanout buffers
>>> + to be physically contiguous. LS2K1000/LS2K0500 is a SOC, only system
>>> + memory is available. LS7A1000/LS7A2000 is bridge chip which is equipped
>>> + with a dedicated video RAM which is 64MB or more, precise size can be
>>> + read from the PCI BAR 2 of the GPU device(0x0014:0x7A15) in the bridge
>>> + chip.
>>> +
>>> + LSDC has two display pipes, each way has a DVO interface which provide
>>> + RGB888 signals, vertical & horizontal synchronisations, data enable and
>>> + the pixel clock. LSDC has two CRTC, each CRTC is able to scanout from
>>> + 1920x1080 resolution at 60Hz. Each CRTC has two FB address registers.
>>> +
>>> + For LS7A1000, there are 4 dedicated GPIOs whose control register is
>>> + located at the DC register space. They are used to emulate two way i2c,
>>> + One for DVO0, another for DVO1.
>>> +
>>> + LS2K1000 and LS2K0500 SoC grab i2c adapter from other module, either
>>> + general purpose GPIO emulated i2c or hardware i2c in the SoC.
>>> +
>>> + LSDC's display pipeline have several components as below description,
>>> +
>>> + The display controller in LS7A1000:
>>> + ___________________ _________
>>> + | -------| | |
>>> + | CRTC0 --> | DVO0 ----> Encoder0 ---> Connector0 ---> | Monitor |
>>> + | _ _ -------| ^ ^ |_________|
>>> + | | | | | -------| | |
>>> + | |_| |_| | i2c0 <--------+-------------+
>>> + | -------|
>>> + | DC IN LS7A1000 |
>>> + | _ _ -------|
>>> + | | | | | | i2c1 <--------+-------------+
>>> + | |_| |_| -------| | | _________
>>> + | -------| | | | |
>>> + | CRTC1 --> | DVO1 ----> Encoder1 ---> Connector1 ---> | Panel |
>>> + | -------| |_________|
>>> + |___________________|
>>> +
>>> + Simple usage of LS7A1000 with LS3A4000 CPU:
>>> +
>>> + +------+ +------------------------------------+
>>> + | DDR4 | | +-------------------+ |
>>> + +------+ | | PCIe Root complex | LS7A1000 |
>>> + || MC0 | +--++---------++----+ |
>>> + +----------+ HT 3.0 | || || |
>>> + | LS3A4000 |<-------->| +---++---+ +--++--+ +---------+ +------+
>>> + | CPU |<-------->| | GC1000 | | LSDC |<--->| DDR3 MC |<->| VRAM |
>>> + +----------+ | +--------+ +-+--+-+ +---------+ +------+
>>> + || MC1 +---------------|--|-----------------+
>>> + +------+ | |
>>> + | DDR4 | +-------+ DVO0 | | DVO1 +------+
>>> + +------+ VGA <--|ADV7125|<--------+ +-------->|TFP410|--> DVI/HDMI
>>> + +-------+ +------+
>>> +
>>> + The display controller in LS2K1000/LS2K0500:
>>> + ___________________ _________
>>> + | -------| | |
>>> + | CRTC0 --> | DVO0 ----> Encoder0 ---> Connector0 ---> | Monitor |
>>> + | _ _ -------| ^ ^ |_________|
>>> + | | | | | | | |
>>> + | |_| |_| | +------+ |
>>> + | <---->| i2c0 |<---------+
>>> + | DC IN LS2K1000 | +------+
>>> + | _ _ | +------+
>>> + | | | | | <---->| i2c1 |----------+
>>> + | |_| |_| | +------+ | _________
>>> + | -------| | | | |
>>> + | CRTC1 --> | DVO1 ----> Encoder1 ---> Connector1 ---> | Panel |
>>> + | -------| |_________|
>>> + |___________________|
>>> +
>>> +properties:
>>> + $nodename:
>>> + pattern: "^display-controller@[0-9a-f],[0-9a-f]$"
>>> +
>>> + compatible:
>>> + oneOf:
>>> + - items:
>>> + - enum:
>>> + - loongson,ls7a1000-dc
>>> + - loongson,ls2k1000-dc
>>> + - loongson,ls2k0500-dc
>>> +
>>> + reg:
>>> + maxItems: 1
>>> +
>>> + interrupts:
>>> + maxItems: 1
>>> +
>>> + '#address-cells':
>>> + const: 1
>>> +
>>> + '#size-cells':
>>> + const: 0
>>> +
>>> + i2c at 6:
>> NAK on made-up bus numbers. See v11 discussion for details.
>>
>> Rob
>
> I am worry about when this driver is loaded before the hardware i2c(on
> the ls7a1000 bridge) driver,
That’s the problem that EPROBE_DEFER addressed.
>
> and when there is no DT support. in such a case, if i2c bus number is
> dynamically assigned,
>
> it may incurring troubles. Made the bus number fixed is benefit to the
> whole system.
>
> DT serve as a purpose to passing parameters to the kernel. bus numbers
> just a kind of parameters.
>
> this is my understanding toward DT. why you are so disagree about this?
> what's the benefits of
>
> disallow put bus numbers it DT? to the whole world of developers who is
> using DT?
There is nothing more to discuss.
You lack understanding to the fundamentals of the DT because you didn’t work
on thousands of platforms and being trapped by previous design failures.
Just follow the instructions from Rob, he is the expert. Is it that hard?
Thanks
--
- Jiaxun
More information about the dri-devel
mailing list