[Intel-gfx] [PATCH v3 4/5] drm/i915/pvc: Add new BCS engines to GuC engine list

Matt Atwood matthew.s.atwood at intel.com
Tue May 24 18:38:36 UTC 2022


On Tue, May 10, 2022 at 11:02:27PM -0700, Matt Roper wrote:
> Intialize ADS system info to reflect the availablity of new BCS engines
> 
> Original-author: CQ Tang
> Cc: Stuart Summers <stuart.summers at intel.com>
> Cc: John Harrison <John.C.Harrison at Intel.com>
Reviewed-by: Matt Atwood <matthew.s.atwood at intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper at intel.com>
> ---
>  drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 2 +-
>  drivers/gpu/drm/i915/i915_drv.h            | 2 ++
>  2 files changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> index 3eabf4cf8eec..bb197610fd5b 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> @@ -457,7 +457,7 @@ static void fill_engine_enable_masks(struct intel_gt *gt,
>  {
>  	info_map_write(info_map, engine_enabled_masks[GUC_RENDER_CLASS], RCS_MASK(gt));
>  	info_map_write(info_map, engine_enabled_masks[GUC_COMPUTE_CLASS], CCS_MASK(gt));
> -	info_map_write(info_map, engine_enabled_masks[GUC_BLITTER_CLASS], 1);
> +	info_map_write(info_map, engine_enabled_masks[GUC_BLITTER_CLASS], BCS_MASK(gt));
>  	info_map_write(info_map, engine_enabled_masks[GUC_VIDEO_CLASS], VDBOX_MASK(gt));
>  	info_map_write(info_map, engine_enabled_masks[GUC_VIDEOENHANCE_CLASS], VEBOX_MASK(gt));
>  }
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 54e9c2a5493d..4b147fd90ec4 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1223,6 +1223,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>  })
>  #define RCS_MASK(gt) \
>  	ENGINE_INSTANCES_MASK(gt, RCS0, I915_MAX_RCS)
> +#define BCS_MASK(gt) \
> +	ENGINE_INSTANCES_MASK(gt, BCS0, I915_MAX_BCS)
>  #define VDBOX_MASK(gt) \
>  	ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS)
>  #define VEBOX_MASK(gt) \
> -- 
> 2.35.1
> 


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