[PATCH v1 1/5] arm64: dts: qcom: sm8450: add RPMH_REGULATOR_LEVEL_LOW_SVS_D1
Dmitry Baryshkov
dmitry.baryshkov at linaro.org
Fri Nov 4 13:13:54 UTC 2022
Add another power saving state used on SM8450. Unfortunately adding it
in proper place causes renumbering of all the opp states in sm8450.dtsi
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov at linaro.org>
---
arch/arm64/boot/dts/qcom/sm8450.dtsi | 20 ++++++++++++--------
include/dt-bindings/power/qcom-rpmpd.h | 1 +
2 files changed, 13 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index eeff62d0954b..250e6b883ca3 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -3197,35 +3197,39 @@ rpmhpd_opp_min_svs: opp2 {
opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
};
- rpmhpd_opp_low_svs: opp3 {
+ rpmhpd_opp_low_svs_d1: opp3 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
+ };
+
+ rpmhpd_opp_low_svs: opp4 {
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
};
- rpmhpd_opp_svs: opp4 {
+ rpmhpd_opp_svs: opp5 {
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
};
- rpmhpd_opp_svs_l1: opp5 {
+ rpmhpd_opp_svs_l1: opp6 {
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
};
- rpmhpd_opp_nom: opp6 {
+ rpmhpd_opp_nom: opp7 {
opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
};
- rpmhpd_opp_nom_l1: opp7 {
+ rpmhpd_opp_nom_l1: opp8 {
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
};
- rpmhpd_opp_nom_l2: opp8 {
+ rpmhpd_opp_nom_l2: opp9 {
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
};
- rpmhpd_opp_turbo: opp9 {
+ rpmhpd_opp_turbo: opp10 {
opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
};
- rpmhpd_opp_turbo_l1: opp10 {
+ rpmhpd_opp_turbo_l1: opp11 {
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
};
};
diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h
index 578e060890dd..69aef395d85b 100644
--- a/include/dt-bindings/power/qcom-rpmpd.h
+++ b/include/dt-bindings/power/qcom-rpmpd.h
@@ -168,6 +168,7 @@
/* SDM845 Power Domain performance levels */
#define RPMH_REGULATOR_LEVEL_RETENTION 16
#define RPMH_REGULATOR_LEVEL_MIN_SVS 48
+#define RPMH_REGULATOR_LEVEL_LOW_SVS_D1 56
#define RPMH_REGULATOR_LEVEL_LOW_SVS 64
#define RPMH_REGULATOR_LEVEL_SVS 128
#define RPMH_REGULATOR_LEVEL_SVS_L0 144
--
2.35.1
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