[PATCH 2/2] drm/i915/mtl: Enable Idle Messaging for GSC CS

[Belgaumkar, Vinay]

On 10/31/2022 8:36 PM, Badal Nilawar wrote:
> From: Vinay Belgaumkar <vinay.belgaumkar at intel.com>
>
> By defaut idle mesaging is disabled for GSC CS so to unblock RC6
> entry on media tile idle messaging need to be enabled.
C6 entry instead of RC6. Also *needs*.
>
> Bspec: 71496
>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com>
> Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar at intel.com>
> Signed-off-by: Badal Nilawar <badal.nilawar at intel.com>
> ---
>   drivers/gpu/drm/i915/gt/intel_engine_pm.c | 12 ++++++++++++
>   drivers/gpu/drm/i915/gt/intel_gt_regs.h   |  3 +++
>   2 files changed, 15 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
> index b0a4a2dbe3ee..8d391f8fd861 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
> @@ -15,6 +15,7 @@
>   #include "intel_rc6.h"
>   #include "intel_ring.h"
>   #include "shmem_utils.h"
> +#include "intel_gt_regs.h"
>   
>   static void dbg_poison_ce(struct intel_context *ce)
>   {
> @@ -271,10 +272,21 @@ static const struct intel_wakeref_ops wf_ops = {
>   
>   void intel_engine_init__pm(struct intel_engine_cs *engine)
>   {
> +	struct drm_i915_private *i915 = engine->i915;
>   	struct intel_runtime_pm *rpm = engine->uncore->rpm;
>   
>   	intel_wakeref_init(&engine->wakeref, rpm, &wf_ops);
>   	intel_engine_init_heartbeat(engine);
> +
> +	if (IS_METEORLAKE(i915) && engine->id == GSC0) {
> +		intel_uncore_write(engine->gt->uncore,
> +				   RC_PSMI_CTRL_GSCCS,
> +				   _MASKED_BIT_DISABLE(IDLE_MSG_DISABLE));
> +		drm_dbg(&i915->drm,
> +			"Set GSC CS Idle Reg to: 0x%x",
> +			intel_uncore_read(engine->gt->uncore, RC_PSMI_CTRL_GSCCS));
Do we need the debug print here?
> +	}
> +
>   }
>   
>   /**
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index f4624262dc81..176902a9f2a2 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -908,6 +908,9 @@
>   #define  MSG_IDLE_FW_MASK	REG_GENMASK(13, 9)
>   #define  MSG_IDLE_FW_SHIFT	9
>   
> +#define	RC_PSMI_CTRL_GSCCS	_MMIO(0x11a050)
> +#define	 IDLE_MSG_DISABLE	BIT(0)

Is the alignment off?

Thanks,

Vinay.

> +
>   #define FORCEWAKE_MEDIA_GEN9			_MMIO(0xa270)
>   #define FORCEWAKE_RENDER_GEN9			_MMIO(0xa278)
>