[PATCH v28 04/11] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1
Matthias Brugger
matthias.bgg at gmail.com
Tue Nov 8 17:46:54 UTC 2022
On 07/11/2022 08:22, Nancy.Lin wrote:
> Add mt8195 vdosys1 routing table to the driver data of mtk-mmsys.
>
> Signed-off-by: Nancy.Lin <nancy.lin at mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
> Reviewed-by: Rex-BC Chen <rex-bc.chen at mediatek.com>
> Reviewed-by: CK Hu <ck.hu at mediatek.com>
> Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
> Tested-by: Bo-Chen Chen <rex-bc.chen at mediatek.com>
> ---
> drivers/soc/mediatek/mt8195-mmsys.h | 139 ++++++++++++++++++++++++++++
> drivers/soc/mediatek/mtk-mmsys.c | 10 ++
> 2 files changed, 149 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
> index abfe94a30248..fd7b455bd675 100644
> --- a/drivers/soc/mediatek/mt8195-mmsys.h
> +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> @@ -75,6 +75,70 @@
> #define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 << 16)
> #define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE (3 << 16)
>
> +#define MT8195_VDO1_VPP_MERGE0_P0_SEL_IN 0xf04
> +#define MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0 1
> +
> +#define MT8195_VDO1_VPP_MERGE0_P1_SEL_IN 0xf08
> +#define MT8195_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1 1
> +
> +#define MT8195_VDO1_DISP_DPI1_SEL_IN 0xf10
> +#define MT8195_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT 0
> +
> +#define MT8195_VDO1_DISP_DP_INTF0_SEL_IN 0xf14
> +#define MT8195_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT 0
> +
> +#define MT8195_VDO1_MERGE4_SOUT_SEL 0xf18
> +#define MT8195_MERGE4_SOUT_TO_DPI1_SEL 2
> +#define MT8195_MERGE4_SOUT_TO_DP_INTF0_SEL 3
> +
> +#define MT8195_VDO1_MIXER_IN1_SEL_IN 0xf24
> +#define MT8195_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT 1
> +
> +#define MT8195_VDO1_MIXER_IN2_SEL_IN 0xf28
> +#define MT8195_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT 1
> +
> +#define MT8195_VDO1_MIXER_IN3_SEL_IN 0xf2c
> +#define MT8195_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT 1
> +
> +#define MT8195_VDO1_MIXER_IN4_SEL_IN 0xf30
> +#define MT8195_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT 1
> +
> +#define MT8195_VDO1_MIXER_OUT_SOUT_SEL 0xf34
> +#define MT8195_MIXER_SOUT_TO_MERGE4_ASYNC_SEL 1
> +
> +#define MT8195_VDO1_VPP_MERGE1_P0_SEL_IN 0xf3c
> +#define MT8195_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2 1
> +
> +#define MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL 0xf40
> +#define MT8195_SOUT_TO_MIXER_IN1_SEL 1
> +
> +#define MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL 0xf44
> +#define MT8195_SOUT_TO_MIXER_IN2_SEL 1
> +
> +#define MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL 0xf48
> +#define MT8195_SOUT_TO_MIXER_IN3_SEL 1
> +
> +#define MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL 0xf4c
> +#define MT8195_SOUT_TO_MIXER_IN4_SEL 1
> +
> +#define MT8195_VDO1_MERGE4_ASYNC_SEL_IN 0xf50
> +#define MT8195_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT 1
> +
> +#define MT8195_VDO1_MIXER_IN1_SOUT_SEL 0xf58
> +#define MT8195_MIXER_IN1_SOUT_TO_DISP_MIXER 0
> +
> +#define MT8195_VDO1_MIXER_IN2_SOUT_SEL 0xf5c
> +#define MT8195_MIXER_IN2_SOUT_TO_DISP_MIXER 0
> +
> +#define MT8195_VDO1_MIXER_IN3_SOUT_SEL 0xf60
> +#define MT8195_MIXER_IN3_SOUT_TO_DISP_MIXER 0
> +
> +#define MT8195_VDO1_MIXER_IN4_SOUT_SEL 0xf64
> +#define MT8195_MIXER_IN4_SOUT_TO_DISP_MIXER 0
> +
> +#define MT8195_VDO1_MIXER_SOUT_SEL_IN 0xf68
> +#define MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER 0
> +
> static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
> {
> DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
> @@ -367,4 +431,79 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
> }
> };
>
> +static const struct mtk_mmsys_routes mmsys_mt8195_vdo1_routing_table[] = {
> + {
> + DDP_COMPONENT_MDP_RDMA0, DDP_COMPONENT_MERGE1,
> + MT8195_VDO1_VPP_MERGE0_P0_SEL_IN, GENMASK(0, 0),
> + MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0
> + }, {
> + DDP_COMPONENT_MDP_RDMA1, DDP_COMPONENT_MERGE1,
> + MT8195_VDO1_VPP_MERGE0_P1_SEL_IN, GENMASK(0, 0),
> + MT8195_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1
> + }, {
> + DDP_COMPONENT_MDP_RDMA2, DDP_COMPONENT_MERGE2,
> + MT8195_VDO1_VPP_MERGE1_P0_SEL_IN, GENMASK(0, 0),
> + MT8195_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2
> + }, {
> + DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER,
> + MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL, GENMASK(1, 0),
> + MT8195_SOUT_TO_MIXER_IN1_SEL
> + }, {
> + DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER,
> + MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL, GENMASK(1, 0),
> + MT8195_SOUT_TO_MIXER_IN2_SEL
> + }, {
> + DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER,
> + MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL, GENMASK(1, 0),
> + MT8195_SOUT_TO_MIXER_IN3_SEL
> + }, {
> + DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER,
> + MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL, GENMASK(1, 0),
> + MT8195_SOUT_TO_MIXER_IN4_SEL
> + }, {
> + DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
> + MT8195_VDO1_MIXER_OUT_SOUT_SEL, GENMASK(0, 0),
> + MT8195_MIXER_SOUT_TO_MERGE4_ASYNC_SEL
> + }, {
> + DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER,
> + MT8195_VDO1_MIXER_IN1_SEL_IN, GENMASK(0, 0),
> + MT8195_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT
> + }, {
> + DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER,
> + MT8195_VDO1_MIXER_IN2_SEL_IN, GENMASK(0, 0),
> + MT8195_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT
> + }, {
> + DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER,
> + MT8195_VDO1_MIXER_IN3_SEL_IN, GENMASK(0, 0),
> + MT8195_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT
> + }, {
> + DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER,
> + MT8195_VDO1_MIXER_IN4_SEL_IN, GENMASK(0, 0),
> + MT8195_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT
> + }, {
> + DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
> + MT8195_VDO1_MIXER_SOUT_SEL_IN, GENMASK(2, 0),
> + MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER
> + }, {
> + DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
> + MT8195_VDO1_MERGE4_ASYNC_SEL_IN, GENMASK(2, 0),
> + MT8195_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT
> + }, {
> + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
> + MT8195_VDO1_DISP_DPI1_SEL_IN, GENMASK(1, 0),
> + MT8195_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT
> + }, {
> + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
> + MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0),
> + MT8195_MERGE4_SOUT_TO_DPI1_SEL
> + }, {
> + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
> + MT8195_VDO1_DISP_DP_INTF0_SEL_IN, GENMASK(1, 0),
> + MT8195_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT
> + }, {
> + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
> + MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0),
> + MT8195_MERGE4_SOUT_TO_DP_INTF0_SEL
> + }
> +};
> #endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
> index 146a78ba06c1..9a327eb5d9d7 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -80,6 +80,12 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
> .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> };
>
> +static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
> + .clk_driver = "clk-mt8195-vdo1",
> + .routes = mmsys_mt8195_vdo1_routing_table,
> + .num_routes = ARRAY_SIZE(mmsys_mt8195_vdo1_routing_table),
> +};
> +
> static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
> .clk_driver = "clk-mt8365-mm",
> .routes = mt8365_mmsys_routing_table,
> @@ -292,6 +298,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
> .compatible = "mediatek,mt8195-vdosys0",
> .data = &mt8195_vdosys0_driver_data,
It seems we are missing a patch in the series. vdosys0 also correct was never
introduced in the driver...
> },
> + {
> + .compatible = "mediatek,mt8195-vdosys1",
> + .data = &mt8195_vdosys1_driver_data,
> + },
> {
> .compatible = "mediatek,mt8365-mmsys",
> .data = &mt8365_mmsys_driver_data,
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