[bug report] drm: rcar-du: Add RZ/G2L DSI driver

Biju Das biju.das.jz at bp.renesas.com
Fri Nov 18 15:20:29 UTC 2022


Hi Dan Carpenter,

Thanks for the feedback.

> Subject: [bug report] drm: rcar-du: Add RZ/G2L DSI driver
> 
> Hello Biju Das,
> 
> The patch 7a043f978ed1: "drm: rcar-du: Add RZ/G2L DSI driver" from Sep
> 20, 2022, leads to the following Smatch static checker warning:
> 
> 	drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c:372
> rzg2l_mipi_dsi_set_display_timing()
> 	warn: uninitialized special assign 'vich1ppsetr |= (1 << 15)'
> 
> drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c
>     347 static void rzg2l_mipi_dsi_set_display_timing(struct
> rzg2l_mipi_dsi *dsi,
>     348                                               const struct
> drm_display_mode *mode)
>     349 {
>     350         u32 vich1ppsetr;
>     351         u32 vich1vssetr;
>     352         u32 vich1vpsetr;
>     353         u32 vich1hssetr;
>     354         u32 vich1hpsetr;
>     355         int dsi_format;
>     356         u32 delay[2];
>     357         u8 index;
>     358
>     359         /* Configuration for Pixel Packet */
>     360         dsi_format = mipi_dsi_pixel_format_to_bpp(dsi->format);
>     361         switch (dsi_format) {
>     362         case 24:
>     363                 vich1ppsetr = VICH1PPSETR_DT_RGB24;
>     364                 break;
>     365         case 18:
>     366                 vich1ppsetr = VICH1PPSETR_DT_RGB18;
>     367                 break;
> 
> What if mipi_dsi_pixel_format_to_bpp() returns 16?

This condition is already validated in rzg2l_mipi_dsi_host_attach(). For val of 16,
It returns error. See line 623.

default:                                                                 
                dev_err(dsi->dev, "Unsupported format 0x%04x\n", device->format);
                 return -EINVAL; 

Cheers,
Biju  

> 
>     368         }
>     369
>     370         if ((dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
> &&
>     371             !(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST))
> --> 372                 vich1ppsetr |= VICH1PPSETR_TXESYNC_PULSE;
>                         ^^^^^^^^^^^
> Uninitialized.
> 
>     373
>     374         rzg2l_mipi_dsi_link_write(dsi, VICH1PPSETR,
> vich1ppsetr);
> 
> regards,
> dan carpenter


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