[PATCH v4 05/11] dt-bindings: display/msm: add support for the display on SM8450
Dmitry Baryshkov
dmitry.baryshkov at linaro.org
Wed Nov 23 10:38:25 UTC 2022
On 23/11/2022 12:32, Krzysztof Kozlowski wrote:
> On 23/11/2022 00:12, Dmitry Baryshkov wrote:
>> Add DPU and MDSS schemas to describe MDSS and DPU blocks on the Qualcomm
>> SM8450 platform.
>>
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov at linaro.org>
>> ---
>> .../bindings/display/msm/qcom,sm8450-dpu.yaml | 139 +++++++
>> .../display/msm/qcom,sm8450-mdss.yaml | 352 ++++++++++++++++++
>> 2 files changed, 491 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml
>> create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml
>>
>
>
>> diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml
>> new file mode 100644
>> index 000000000000..8e25d456e5e9
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml
>> @@ -0,0 +1,139 @@
>> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/display/msm/qcom,sm8450-dpu.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Qualcomm SM8450 Display DPU
>> +
>> +maintainers:
>> + - Dmitry Baryshkov <dmitry.baryshkov at linaro.org>
>> +
>> +$ref: /schemas/display/msm/dpu-common.yaml#
>> +
>> +properties:
>> + compatible:
>> + const: qcom,sm8450-dpu
>> +
>> + reg:
>> + items:
>> + - description: Address offset and size for mdp register set
>> + - description: Address offset and size for vbif register set
>> +
>> + reg-names:
>> + items:
>> + - const: mdp
>> + - const: vbif
>> +
>> + clocks:
>> + items:
>> + - description: Display hf axi clock
>> + - description: Display sf axi clock
>> + - description: Display ahb clock
>> + - description: Display lut clock
>> + - description: Display core clock
>> + - description: Display vsync clock
>> +
>> + clock-names:
>> + items:
>> + - const: bus
>> + - const: nrt_bus
>> + - const: iface
>> + - const: lut
>> + - const: core
>> + - const: vsync
>> +
>> +required:
>> + - compatible
>> + - reg
>> + - reg-names
>> + - clocks
>> + - clock-names
>> +
>> +unevaluatedProperties: false
>> +
>> +examples:
>> + - |
>> + #include <dt-bindings/clock/qcom,sm8450-dispcc.h>
>> + #include <dt-bindings/clock/qcom,gcc-sm8450.h>
>> + #include <dt-bindings/interrupt-controller/arm-gic.h>
>> + #include <dt-bindings/interconnect/qcom,sm8450.h>
>> + #include <dt-bindings/power/qcom-rpmpd.h>
>> +
>> + display-controller at ae01000 {
>> + compatible = "qcom,sm8450-dpu";
>> + reg = <0x0ae01000 0x8f000>,
>> + <0x0aeb0000 0x2008>;
>> + reg-names = "mdp", "vbif";
>> +
>> + clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
>> + <&gcc GCC_DISP_SF_AXI_CLK>,
>> + <&dispcc DISP_CC_MDSS_AHB_CLK>,
>> + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
>> + <&dispcc DISP_CC_MDSS_MDP_CLK>,
>> + <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
>> + clock-names = "bus",
>> + "nrt_bus",
>> + "iface",
>> + "lut",
>> + "core",
>> + "vsync";
>> +
>> + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
>> + assigned-clock-rates = <19200000>;
>> +
>> + operating-points-v2 = <&mdp_opp_table>;
>> + power-domains = <&rpmhpd SM8450_MMCX>;
>> +
>> + interrupt-parent = <&mdss>;
>> + interrupts = <0>;
>> +
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port at 0 {
>> + reg = <0>;
>> + dpu_intf1_out: endpoint {
>> + remote-endpoint = <&dsi0_in>;
>> + };
>> + };
>> +
>> + port at 1 {
>> + reg = <1>;
>> + dpu_intf2_out: endpoint {
>> + remote-endpoint = <&dsi1_in>;
>> + };
>> + };
>> + };
>> +
>> + mdp_opp_table: opp-table {
>> + compatible = "operating-points-v2";
>> +
>> + opp-172000000{
>> + opp-hz = /bits/ 64 <172000000>;
>> + required-opps = <&rpmhpd_opp_low_svs_d1>;
>> + };
>> +
>> + opp-200000000 {
>> + opp-hz = /bits/ 64 <200000000>;
>> + required-opps = <&rpmhpd_opp_low_svs>;
>> + };
>> +
>> + opp-325000000 {
>> + opp-hz = /bits/ 64 <325000000>;
>> + required-opps = <&rpmhpd_opp_svs>;
>> + };
>> +
>> + opp-375000000 {
>> + opp-hz = /bits/ 64 <375000000>;
>> + required-opps = <&rpmhpd_opp_svs_l1>;
>> + };
>> +
>> + opp-500000000 {
>> + opp-hz = /bits/ 64 <500000000>;
>> + required-opps = <&rpmhpd_opp_nom>;
>> + };
>> + };
>> + };
>> +...
>> diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml
>> new file mode 100644
>> index 000000000000..73f8c5caf637
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml
>> @@ -0,0 +1,352 @@
>> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/display/msm/qcom,sm8450-mdss.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Qualcomm SM8450 Display MDSS
>> +
>> +maintainers:
>> + - Dmitry Baryshkov <dmitry.baryshkov at linaro.org>
>> +
>> +description:
>> + Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
>> + sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
>> + bindings of MDSS are mentioned for SM8450 target.
>> +
>> +$ref: /schemas/display/msm/mdss-common.yaml#
>> +
>> +properties:
>> + compatible:
>> + items:
>
> I don't understand this patchset. Some tags were present, then gone.
> Items was never here, now it is... and you explicitly received such
> feedback long time ago, therefore I suspect you sent or rebased
> something old.
>
> Go through all previous comments.
Let me check, what went wrong on my side.
>
>> + - const: qcom,sm8450-mdss
>> +
>
> Best regards,
> Krzysztof
>
--
With best wishes
Dmitry
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