[PATCH v2 02/12] dt-bindings: display: msm: Add qcom, sm8350-mdss binding
Robert Foss
robert.foss at linaro.org
Tue Nov 29 11:31:46 UTC 2022
On Tue, 15 Nov 2022 at 17:49, Rob Herring <robh at kernel.org> wrote:
>
> On Tue, Nov 15, 2022 at 12:17:11PM +0100, Robert Foss wrote:
> > Mobile Display Subsystem (MDSS) encapsulates sub-blocks
> > like DPU display controller, DSI etc. Add YAML schema for MDSS device
> > tree bindings
> >
> > Signed-off-by: Robert Foss <robert.foss at linaro.org>
> > ---
> > .../display/msm/qcom,sm8350-mdss.yaml | 240 ++++++++++++++++++
> > 1 file changed, 240 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml
> > new file mode 100644
> > index 000000000000..9a0694853576
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml
> > @@ -0,0 +1,240 @@
> > +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/display/msm/qcom,sm8350-mdss.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Qualcomm SM8350 Display MDSS
> > +
> > +maintainers:
> > + - Robert Foss <robert.foss at linaro.org>
> > +
> > +description:
> > + Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
>
> Drop 'Device tree bindings for '. Describe what this h/w is.
Ack
>
> > + sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
> > + bindings of MDSS are mentioned for SM8350 target.
> > +
> > +$ref: /schemas/display/msm/mdss-common.yaml#
> > +
> > +properties:
> > + compatible:
> > + items:
> > + - const: qcom,sm8350-mdss
> > +
> > + clocks:
> > + items:
> > + - description: Display AHB clock from gcc
> > + - description: Display hf axi clock
> > + - description: Display sf axi clock
> > + - description: Display core clock
> > +
> > + clock-names:
> > + items:
> > + - const: iface
> > + - const: bus
> > + - const: nrt_bus
> > + - const: core
> > +
> > + iommus:
> > + maxItems: 1
> > +
> > + interconnects:
> > + maxItems: 2
> > +
> > + interconnect-names:
> > + maxItems: 2
>
> Need to define the names.
>
> > +
> > +patternProperties:
> > + "^display-controller@[0-9a-f]+$":
> > + type: object
> > + properties:
> > + compatible:
> > + const: qcom,sm8350-dpu
> > +
> > + "^dsi@[0-9a-f]+$":
> > + type: object
> > + properties:
> > + compatible:
> > + const: qcom,mdss-dsi-ctrl
> > +
> > + "^phy@[0-9a-f]+$":
> > + type: object
> > + properties:
> > + compatible:
> > + const: qcom,dsi-phy-5nm-8350
> > +
> > +unevaluatedProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/clock/qcom,dispcc-sm8350.h>
> > + #include <dt-bindings/clock/qcom,gcc-sm8350.h>
> > + #include <dt-bindings/clock/qcom,rpmh.h>
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > + #include <dt-bindings/interconnect/qcom,sm8350.h>
> > + #include <dt-bindings/power/qcom-rpmpd.h>
> > +
> > + display-subsystem at ae00000 {
> > + compatible = "qcom,sm8350-mdss";
> > + reg = <0x0ae00000 0x1000>;
> > + reg-names = "mdss";
> > +
> > + interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
> > + <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
> > + interconnect-names = "mdp0-mem", "mdp1-mem";
> > +
> > + power-domains = <&dispcc MDSS_GDSC>;
> > + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
> > +
> > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> > + <&gcc GCC_DISP_HF_AXI_CLK>,
> > + <&gcc GCC_DISP_SF_AXI_CLK>,
> > + <&dispcc DISP_CC_MDSS_MDP_CLK>;
> > + clock-names = "iface", "bus", "nrt_bus", "core";
> > +
> > + iommus = <&apps_smmu 0x820 0x402>;
> > +
> > + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-controller;
> > + #interrupt-cells = <1>;
> > +
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + ranges;
> > +
> > + display-controller at ae01000 {
> > + compatible = "qcom,sm8350-dpu";
> > + reg = <0x0ae01000 0x8f000>,
> > + <0x0aeb0000 0x2008>;
> > + reg-names = "mdp", "vbif";
> > +
> > + clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
> > + <&gcc GCC_DISP_SF_AXI_CLK>,
> > + <&dispcc DISP_CC_MDSS_AHB_CLK>,
> > + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
> > + <&dispcc DISP_CC_MDSS_MDP_CLK>,
> > + <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
> > + clock-names = "bus",
> > + "nrt_bus",
> > + "iface",
> > + "lut",
> > + "core",
> > + "vsync";
> > +
> > + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
> > + assigned-clock-rates = <19200000>;
> > +
> > + operating-points-v2 = <&mdp_opp_table>;
> > + power-domains = <&rpmhpd SM8350_MMCX>;
> > +
> > + interrupt-parent = <&mdss>;
> > + interrupts = <0>;
> > +
> > + ports {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + port at 0 {
> > + reg = <0>;
> > + dpu_intf1_out: endpoint {
> > + remote-endpoint = <&dsi0_in>;
> > + };
> > + };
> > + };
> > +
> > + mdp_opp_table: opp-table {
> > + compatible = "operating-points-v2";
> > +
> > + opp-200000000 {
> > + opp-hz = /bits/ 64 <200000000>;
> > + required-opps = <&rpmhpd_opp_low_svs>;
> > + };
> > +
> > + opp-300000000 {
> > + opp-hz = /bits/ 64 <300000000>;
> > + required-opps = <&rpmhpd_opp_svs>;
> > + };
> > +
> > + opp-345000000 {
> > + opp-hz = /bits/ 64 <345000000>;
> > + required-opps = <&rpmhpd_opp_svs_l1>;
> > + };
> > +
> > + opp-460000000 {
> > + opp-hz = /bits/ 64 <460000000>;
> > + required-opps = <&rpmhpd_opp_nom>;
> > + };
> > + };
> > + };
> > +
> > + dsi0: dsi at ae94000 {
> > + compatible = "qcom,mdss-dsi-ctrl";
> > + reg = <0x0ae94000 0x400>;
> > + reg-names = "dsi_ctrl";
> > +
> > + interrupt-parent = <&mdss>;
> > + interrupts = <4>;
> > +
> > + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
> > + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
> > + <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
> > + <&dispcc DISP_CC_MDSS_ESC0_CLK>,
> > + <&dispcc DISP_CC_MDSS_AHB_CLK>,
> > + <&gcc GCC_DISP_HF_AXI_CLK>;
> > + clock-names = "byte",
> > + "byte_intf",
> > + "pixel",
> > + "core",
> > + "iface",
> > + "bus";
> > +
> > + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
> > + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
> > + assigned-clock-parents = <&dsi0_phy 0>,
> > + <&dsi0_phy 1>;
> > +
> > + operating-points-v2 = <&dsi_opp_table>;
> > + power-domains = <&rpmhpd SM8350_MMCX>;
> > +
> > + phys = <&dsi0_phy>;
> > + phy-names = "dsi";
> > +
> > + ports {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + port at 0 {
> > + reg = <0>;
> > + dsi0_in: endpoint {
> > + remote-endpoint = <&dpu_intf1_out>;
> > + };
> > + };
> > +
> > + port at 1 {
> > + reg = <1>;
> > + dsi0_out: endpoint {
> > + };
> > + };
> > + };
> > + };
> > +
> > + dsi0_phy: phy at ae94400 {
>
> I assume the phy has its own example somewhere else and its not really
> relevant to this binding. So drop.
Ack.
>
> > + compatible = "qcom,dsi-phy-5nm-8350";
> > + reg = <0x0ae94400 0x200>,
> > + <0x0ae94600 0x280>,
> > + <0x0ae94900 0x260>;
> > + reg-names = "dsi_phy",
> > + "dsi_phy_lane",
> > + "dsi_pll";
> > +
> > + #clock-cells = <1>;
> > + #phy-cells = <0>;
> > +
> > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> > + <&rpmhcc RPMH_CXO_CLK>;
> > + clock-names = "iface", "ref";
> > +
> > + vdds-supply = <&vreg_l5b_0p88>;
> > + };
> > + };
> > +...
> > --
> > 2.34.1
> >
> >
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