[RFC PATCH 1/1] drm/bridge: ti-sn65dsi83: Remove burst mode

Marek Vasut marex at denx.de
Tue Oct 4 12:15:43 UTC 2022


On 10/4/22 13:57, estl at gmx.net wrote:
> From: Eberhard Stoll <eberhard.stoll at kontron.de>
> 
> Remove LVDS panel overclocking for some configurations by disabling
> burst mode for this chip
> 
> With burst mode enabled, some DSI controllers increase their DSI lane
> clock beyond the clock which is needed to transfer all pixel data.
> 
> But this driver operates with a pixel clock derived from the DSI lane
> clock by a fixed prescaler. So, every increase of the DSI clock also
> increases the LVDS pixel clock. In this case, the LVDS pixel clock is
> overclocked.
> 
> This is the case e.g. for synopsys stm DSI bridge
> (drm/stm/dw_mipi_dsi-stm.c). With burst mode the DSI clock is
> increased by 20% and therefore also for the LVDS panel.
> 
> Signed-off-by: Eberhard Stoll <eberhard.stoll at kontron.de>
> ---
>   drivers/gpu/drm/bridge/ti-sn65dsi83.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi83.c b/drivers/gpu/drm/bridge/ti-sn65dsi83.c
> index c901c0e1a3b0..ffc39208536e 100644
> --- a/drivers/gpu/drm/bridge/ti-sn65dsi83.c
> +++ b/drivers/gpu/drm/bridge/ti-sn65dsi83.c
> @@ -272,7 +272,7 @@ static int sn65dsi83_attach(struct drm_bridge *bridge,
> 
>   	dsi->lanes = ctx->dsi_lanes;
>   	dsi->format = MIPI_DSI_FMT_RGB888;
> -	dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST;
> +	dsi->mode_flags = MIPI_DSI_MODE_VIDEO;
> 
>   	ret = mipi_dsi_attach(dsi);
>   	if (ret < 0) {

The burst mode is the most efficient mode, so please keep it. This patch 
is the wrong approach.

The problem with DSI HS clock is known and long standing, I tried to 
solve it twice, but neither solution made it in. It is probably a good 
idea to read through the suggestions and try to follow the latest one by 
negotiating the link clock via bridge state:

https://lore.kernel.org/dri-devel/20220801131113.182487-1-marex@denx.de/
https://lore.kernel.org/all/20220219002844.362157-1-marex@denx.de/


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