[PATCH 2/4] drm/i915/mtl: Modify CAGF functions for MTL

[Rodrigo Vivi]

On Tue, Oct 18, 2022 at 10:20:41PM -0700, Ashutosh Dixit wrote:
> From: Badal Nilawar <badal.nilawar at intel.com>
> 
> Update CAGF functions for MTL to get actual resolved frequency of 3D and
> SAMedia.
> 
> v2: Update MTL_MIRROR_TARGET_WP1 position/formatting (MattR)
>     Move MTL branches in cagf functions to top (MattR)
>     Fix commit message (Andi)
> v3: Added comment about registers not needing forcewake for Gen12+ and
>     returning 0 freq in RC6
> 
> Bspec: 66300
> 
> Signed-off-by: Ashutosh Dixit <ashutosh.dixit at intel.com>
> Signed-off-by: Badal Nilawar <badal.nilawar at intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_gt_regs.h |  4 ++++
>  drivers/gpu/drm/i915/gt/intel_rps.c     | 12 ++++++++++--
>  2 files changed, 14 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index a7a0129d0e3fc..b4b1b54ad738f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -21,6 +21,10 @@
>   */
>  #define PERF_REG(offset)			_MMIO(offset)
>  
> +/* MTL workpoint reg to get core C state and actual freq of 3D, SAMedia */
> +#define MTL_MIRROR_TARGET_WP1			_MMIO(0xc60)
> +#define   MTL_CAGF_MASK				REG_GENMASK(8, 0)
> +
>  /* RPM unit config (Gen8+) */
>  #define RPM_CONFIG0				_MMIO(0xd00)
>  #define   GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT	3
> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
> index df21258976d86..5a743ae4dd11e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rps.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
> @@ -2093,7 +2093,9 @@ u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat)
>  	struct drm_i915_private *i915 = rps_to_i915(rps);
>  	u32 cagf;
>  
> -	if (GRAPHICS_VER(i915) >= 12)
> +	if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
> +		cagf = rpstat & MTL_CAGF_MASK;

I believe we should advocate more the use of the REG_FIELD_GET

  cagf = REG_FIELD_GET(MTL_CAGF_MASK, rpstat);

> +	else if (GRAPHICS_VER(i915) >= 12)
>  		cagf = (rpstat & GEN12_CAGF_MASK) >> GEN12_CAGF_SHIFT;

cagf = REG_FIELD_GET(GEN12_CAGF_MASK, rpstat);
// witht the proper REG_GENAMSK usage on the gen12_cagf_mask...

>  	else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
>  		cagf = (rpstat >> 8) & 0xff;

 #define RPE_MASK REG_GENMASK(15, 8)
         cagf = REG_FIELD_GET(RPE_MASK, rpstat)


> @@ -2116,7 +2118,13 @@ static u32 read_cagf(struct intel_rps *rps)
>  	struct intel_uncore *uncore = rps_to_uncore(rps);
                            ^

>  	u32 freq;
>  
> -	if (GRAPHICS_VER(i915) >= 12) {
> +	/*
> +	 * For Gen12+ reading freq from HW does not need a forcewake and
> +	 * registers will return 0 freq when GT is in RC6
> +	 */
> +	if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) {
> +		freq = intel_uncore_read(rps_to_gt(rps)->uncore, MTL_MIRROR_TARGET_WP1);

here we should use directly the local uncore already declared above with the same helper...
and consistent with the following elses...

> +	} else if (GRAPHICS_VER(i915) >= 12) {
>  		freq = intel_uncore_read(uncore, GEN12_RPSTAT1);
>  	} else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
>  		vlv_punit_get(i915);
> -- 
> 2.38.0
>