[PATCH v3 1/2] drm/msm: move domain allocation into msm_iommu_new()

[Dmitry Baryshkov]

On 27/10/2022 18:48, Rob Clark wrote:
> On Tue, Oct 25, 2022 at 1:04 PM Dmitry Baryshkov
> <dmitry.baryshkov at linaro.org> wrote:
>>
>> After the msm_iommu instance is created, the IOMMU domain is completely
>> handled inside the msm_iommu code. Move the iommu_domain_alloc() call
>> into the msm_iommu_new() to simplify callers code.
>>
>> Reported-by: kernel test robot <lkp at intel.com>
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov at linaro.org>
>> ---
>>   drivers/gpu/drm/msm/adreno/a6xx_gmu.c    | 12 +++++-------
>>   drivers/gpu/drm/msm/adreno/a6xx_gpu.c    | 25 +++++++++---------------
>>   drivers/gpu/drm/msm/adreno/adreno_gpu.c  | 25 +++++++++---------------
>>   drivers/gpu/drm/msm/adreno/adreno_gpu.h  |  2 --
>>   drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 19 +++++++++---------
>>   drivers/gpu/drm/msm/msm_drv.c            | 18 ++++++++---------
>>   drivers/gpu/drm/msm/msm_iommu.c          | 20 ++++++++++++++++---
>>   drivers/gpu/drm/msm/msm_mmu.h            |  3 ++-
>>   8 files changed, 60 insertions(+), 64 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
>> index e033d6a67a20..6484b97c5344 100644
>> --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
>> @@ -1213,19 +1213,17 @@ static int a6xx_gmu_memory_alloc(struct a6xx_gmu *gmu, struct a6xx_gmu_bo *bo,
>>
>>   static int a6xx_gmu_memory_probe(struct a6xx_gmu *gmu)
>>   {
>> -       struct iommu_domain *domain;
>>          struct msm_mmu *mmu;
>>
>> -       domain = iommu_domain_alloc(&platform_bus_type);
>> -       if (!domain)
>> +       mmu = msm_iommu_new(gmu->dev, 0);
>> +       if (!mmu)
>>                  return -ENODEV;
>> +       if (IS_ERR(mmu))
>> +               return PTR_ERR(mmu);
>>
>> -       mmu = msm_iommu_new(gmu->dev, domain);
>>          gmu->aspace = msm_gem_address_space_create(mmu, "gmu", 0x0, 0x80000000);
>> -       if (IS_ERR(gmu->aspace)) {
>> -               iommu_domain_free(domain);
>> +       if (IS_ERR(gmu->aspace))
>>                  return PTR_ERR(gmu->aspace);
>> -       }
>>
>>          return 0;
>>   }
>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
>> index fdc578016e0b..7a1b4397b842 100644
>> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
>> @@ -1784,37 +1784,30 @@ static void a6xx_gpu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp,
>>   static struct msm_gem_address_space *
>>   a6xx_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev)
>>   {
>> -       struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
>> -       struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
>> -       struct iommu_domain *iommu;
>>          struct msm_mmu *mmu;
>>          struct msm_gem_address_space *aspace;
>> +       struct iommu_domain_geometry *geometry;
>>          u64 start, size;
>>
>> -       iommu = iommu_domain_alloc(&platform_bus_type);
>> -       if (!iommu)
>> -               return NULL;
>> -
>>          /*
>>           * This allows GPU to set the bus attributes required to use system
>>           * cache on behalf of the iommu page table walker.
>>           */
>> -       if (!IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice))
>> -               adreno_set_llc_attributes(iommu);
>> -
>> -       mmu = msm_iommu_new(&pdev->dev, iommu);
>> -       if (IS_ERR(mmu)) {
>> -               iommu_domain_free(iommu);
>> +       mmu = msm_iommu_new(&pdev->dev, IO_PGTABLE_QUIRK_ARM_OUTER_WBWA);
> 
> I think/assume the quirk still needs to be conditional on
> a6xx_gpu->htw_llc_slice.. or at least I'm not sure what happens if we
> set it but do not have an LLCC (or allocated slice)


Argh, I forgot the check while doing the refactoring. Will fix in v4.


-- 
With best wishes
Dmitry