[PATCH v6 1/3] drm/bridge: ti-sn65dsi86: Reject modes with too large blanking

[Robert Foss]

On Wed, 31 Aug 2022 at 10:27, Tomi Valkeinen
<tomi.valkeinen at ideasonboard.com> wrote:
>
> From: Tomi Valkeinen <tomi.valkeinen+renesas at ideasonboard.com>
>
> The front and back porch registers are 8 bits, and pulse width registers
> are 15 bits, so reject any modes with larger periods.
>
> Signed-off-by: Tomi Valkeinen <tomi.valkeinen+renesas at ideasonboard.com>
> ---
>  drivers/gpu/drm/bridge/ti-sn65dsi86.c | 23 +++++++++++++++++++++++
>  1 file changed, 23 insertions(+)
>
> diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
> index 90bbabde1595..09d3c65fa2ba 100644
> --- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c
> +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
> @@ -747,6 +747,29 @@ ti_sn_bridge_mode_valid(struct drm_bridge *bridge,
>         if (mode->clock > 594000)
>                 return MODE_CLOCK_HIGH;
>
> +       /*
> +        * The front and back porch registers are 8 bits, and pulse width
> +        * registers are 15 bits, so reject any modes with larger periods.
> +        */
> +
> +       if ((mode->hsync_start - mode->hdisplay) > 0xff)
> +               return MODE_HBLANK_WIDE;
> +
> +       if ((mode->vsync_start - mode->vdisplay) > 0xff)
> +               return MODE_VBLANK_WIDE;
> +
> +       if ((mode->hsync_end - mode->hsync_start) > 0x7fff)
> +               return MODE_HSYNC_WIDE;
> +
> +       if ((mode->vsync_end - mode->vsync_start) > 0x7fff)
> +               return MODE_VSYNC_WIDE;
> +
> +       if ((mode->htotal - mode->hsync_end) > 0xff)
> +               return MODE_HBLANK_WIDE;
> +
> +       if ((mode->vtotal - mode->vsync_end) > 0xff)
> +               return MODE_VBLANK_WIDE;
> +
>         return MODE_OK;
>  }
>
> --
> 2.34.1
>


Reviewed-by: Robert Foss <robert.foss at linaro.org>