[PATCH 4/4] drm/bridge: lt8912b: clarify lvds output status

[Adrien Grassein]

Le jeu. 22 sept. 2022 à 14:43, Philippe Schenker <dev at pschenker.ch> a écrit :
>
> From: Francesco Dolcini <francesco.dolcini at toradex.com>
>
> Add comments on the lt8912_write_lvds_config() config to document the
> current settings and to make it clear that this is a hardcoded
> configuration not relevant for the HDMI output (could be removed without
> affecting the HDMI port).
>
> No changes on the actual register writes.
>
> Signed-off-by: Francesco Dolcini <francesco.dolcini at toradex.com>
> Signed-off-by: Philippe Schenker <philippe.schenker at toradex.com>
Acked-by: Adrien Grassein <adrien.grassein at gmail.com>
> ---
>
>  drivers/gpu/drm/bridge/lontium-lt8912b.c | 26 ++++++++++++++++--------
>  1 file changed, 17 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/lontium-lt8912b.c b/drivers/gpu/drm/bridge/lontium-lt8912b.c
> index 5968f4af190b..3e870d45f881 100644
> --- a/drivers/gpu/drm/bridge/lontium-lt8912b.c
> +++ b/drivers/gpu/drm/bridge/lontium-lt8912b.c
> @@ -165,24 +165,32 @@ static int lt8912_write_rxlogicres_config(struct lt8912 *lt)
>         return ret;
>  };
>
> +/* enable LVDS output with some hardcoded configuration, not required for the HDMI output */
>  static int lt8912_write_lvds_config(struct lt8912 *lt)
>  {
>         const struct reg_sequence seq[] = {
> +               // lvds power up
>                 {0x44, 0x30},
>                 {0x51, 0x05},
> -               {0x50, 0x24},
> -               {0x51, 0x2d},
> -               {0x52, 0x04},
> -               {0x69, 0x0e},
> +
> +               // core pll bypass
> +               {0x50, 0x24}, // cp=50uA
> +               {0x51, 0x2d}, // Pix_clk as reference, second order passive LPF PLL
> +               {0x52, 0x04}, // loopdiv=0, use second-order PLL
> +               {0x69, 0x0e}, // CP_PRESET_DIV_RATIO
>                 {0x69, 0x8e},
>                 {0x6a, 0x00},
> -               {0x6c, 0xb8},
> +               {0x6c, 0xb8}, // RGD_CP_SOFT_K_EN,RGD_CP_SOFT_K[13:8]
>                 {0x6b, 0x51},
> -               {0x04, 0xfb},
> +
> +               {0x04, 0xfb}, // core pll reset
>                 {0x04, 0xff},
> -               {0x7f, 0x00},
> -               {0xa8, 0x13},
> -               {0x02, 0xf7},
> +
> +               // scaler bypass
> +               {0x7f, 0x00}, // disable scaler
> +               {0xa8, 0x13}, // 0x13: JEIDA, 0x33: VESA
> +
> +               {0x02, 0xf7}, // lvds pll reset
>                 {0x02, 0xff},
>                 {0x03, 0xcf},
>                 {0x03, 0xff},
> --
> 2.37.3
>