[PATCH] drm/i915/guc: Don't capture Gen8 regs on Gen12 devices

[Matt Roper]

On Mon, Apr 03, 2023 at 02:33:34PM -0700, John.C.Harrison at Intel.com wrote:
> From: John Harrison <John.C.Harrison at Intel.com>
> 
> A pair of pre-Gen12 registers were being included in the Gen12 capture
> list. GuC was rejecting those as being invalid and logging errors
> about them. So, stop doing it.

Looks like these registers existed from gen8-gen11.  With this change,
it looks like they also won't be included in the GuC error capture for
gen11 (ICL and EHL/JSL) since those platforms return xe_lpd_lists [1]
rather than default_lists; do we care about that?  I assume not (since
those platforms don't use GuC submission unless you force it with the
enable_guc modparam and taint your kernel), but I figured I should point
it out.

Reviewed-by: Matt Roper <matthew.d.roper at intel.com>


[1] Why is the main list we use called xe_lpd (i.e., the name of ADL-P's
    display IP)?  It doesn't seem like we're doing anything with display
    registers here so using display IP naming seems really confusing.


Matt

> 
> Signed-off-by: John Harrison <John.C.Harrison at Intel.com>
> Fixes: dce2bd542337 ("drm/i915/guc: Add Gen9 registers for GuC error state capture.")
> Cc: Alan Previn <alan.previn.teres.alexis at intel.com>
> Cc: Umesh Nerlige Ramappa <umesh.nerlige.ramappa at intel.com>
> Cc: Lucas De Marchi <lucas.demarchi at intel.com>
> Cc: John Harrison <John.C.Harrison at Intel.com>
> Cc: Jani Nikula <jani.nikula at intel.com>
> Cc: Matt Roper <matthew.d.roper at intel.com>
> Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan at intel.com>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com>
> ---
>  drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c | 7 +++++--
>  1 file changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
> index cf49188db6a6e..e0e793167d61b 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
> @@ -31,12 +31,14 @@
>  	{ FORCEWAKE_MT,             0,      0, "FORCEWAKE" }
>  
>  #define COMMON_GEN9BASE_GLOBAL \
> -	{ GEN8_FAULT_TLB_DATA0,     0,      0, "GEN8_FAULT_TLB_DATA0" }, \
> -	{ GEN8_FAULT_TLB_DATA1,     0,      0, "GEN8_FAULT_TLB_DATA1" }, \
>  	{ ERROR_GEN6,               0,      0, "ERROR_GEN6" }, \
>  	{ DONE_REG,                 0,      0, "DONE_REG" }, \
>  	{ HSW_GTT_CACHE_EN,         0,      0, "HSW_GTT_CACHE_EN" }
>  
> +#define GEN9_GLOBAL \
> +	{ GEN8_FAULT_TLB_DATA0,     0,      0, "GEN8_FAULT_TLB_DATA0" }, \
> +	{ GEN8_FAULT_TLB_DATA1,     0,      0, "GEN8_FAULT_TLB_DATA1" }
> +
>  #define COMMON_GEN12BASE_GLOBAL \
>  	{ GEN12_FAULT_TLB_DATA0,    0,      0, "GEN12_FAULT_TLB_DATA0" }, \
>  	{ GEN12_FAULT_TLB_DATA1,    0,      0, "GEN12_FAULT_TLB_DATA1" }, \
> @@ -142,6 +144,7 @@ static const struct __guc_mmio_reg_descr xe_lpd_gsc_inst_regs[] = {
>  static const struct __guc_mmio_reg_descr default_global_regs[] = {
>  	COMMON_BASE_GLOBAL,
>  	COMMON_GEN9BASE_GLOBAL,
> +	GEN9_GLOBAL,
>  };
>  
>  static const struct __guc_mmio_reg_descr default_rc_class_regs[] = {
> -- 
> 2.39.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation