[Intel-gfx] [PATCH v2] drm/i915: Make IRQ reset and postinstall multi-gt aware

Tvrtko Ursulin tvrtko.ursulin at linux.intel.com
Thu Apr 13 14:16:34 UTC 2023


On 13/04/2023 14:56, Andi Shyti wrote:
> Hi Tvrtko,
> 
> (I forgot to CC Daniele)
> 
> On Thu, Apr 13, 2023 at 11:41:28AM +0100, Tvrtko Ursulin wrote:
>>
>> On 13/04/2023 10:20, Andi Shyti wrote:
>>> From: Paulo Zanoni <paulo.r.zanoni at intel.com>
>>>
>>> In multitile systems IRQ need to be reset and enabled per GT.
>>>
>>> Although in MTL the GUnit misc interrupts register set are
>>> available only in GT-0, we need to loop through all the GT's
>>> in order to initialize the media engine which lies on a different
>>> GT.
>>>
>>> Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
>>> Cc: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
>>> Signed-off-by: Andi Shyti <andi.shyti at linux.intel.com>
>>> ---
>>> Hi,
>>>
>>> proposing again this patch, apparently GuC needs this patch to
>>> initialize the media GT.
>>
>> What is the resolution for Matt's concern that this is wrong for MTL?
> 
> There are two explanations, one easy and one less easy.
> 
> The easy one: without this patch i915 doesn't boot on MTL!(*)
> 
> The second explanation is that in MTL the media engine has it's
> own set of misc irq's registers and those are on a different GT
> (Daniele pointed this out).
> 
> I sent this patch not to bypass any review, but to restart the
> discussion as this patch was just dropped.

I see. It does not sound too challenging to handle with a little bit of 
refactoring. Move writes engine registers to a helper and add a MTL 
specific reset/postinstall? Then MTL can do the engine ones outside the 
for_each_gt loop and the replicated ones under it. Give or take, I did 
not look into the details.

Regards,

Tvrtko


More information about the dri-devel mailing list