[PATCH v3] drm/msm/dpu: always program DSC active bits

[Marijn Suijten]

On 2023-04-14 09:46:17, Kuogee Hsieh wrote:
> In current code, the dsc active bits are set only if the cfg->dsc is set.

This is the old sentence from v1 again, did you accidentally send the
wrong patch as the improvements from v2 are missing?

> However, for displays which are hot-pluggable, there can be a use-case
> of disconnecting a DSC supported sink and connecting a non-DSC sink.
> 
> For those cases we need to clear DSC active bits during teardown.

At least teardown is one word again, v2 had "tear down" which is wrong.

> As discuss at [1], clear DSC active bit will handled at reset_intf_cfg()

discussed* as pointed out by Dmitry, and make it clear that this is
about clearing CTL_DSC_ACTIVE (and CTL_DSC_FLUSH?) specifically.  Once
that is moved to reset_intf_cfg(), this patch should be reverted as
there is no need to write the registers once again when cfg->dsc equals
0.

- Marijn

> Signed-off-by: Kuogee Hsieh <quic_khsieh at quicinc.com>
> Fixes: 77f6da90487c ("drm/msm/disp/dpu1: Add DSC support in hw_ctl")
> Reviewed-by: Abhinav Kumar <quic_abhinavk at quicinc.com>
> Reviewed-by: Marijn Suijten <marijn.suijten at somainline.org>
> 
> [1] https://lore.kernel.org/linux-arm-msm/ec045d6b-4ffd-0f8c-4011-8db45edc6978@quicinc.com/
> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 7 +++----
>  1 file changed, 3 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> index bbdc95c..88e4efe 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> @@ -541,10 +541,9 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx,
>  	if (cfg->merge_3d)
>  		DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE,
>  			      BIT(cfg->merge_3d - MERGE_3D_0));
> -	if (cfg->dsc) {
> -		DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, DSC_IDX);
> -		DPU_REG_WRITE(c, CTL_DSC_ACTIVE, cfg->dsc);
> -	}
> +
> +	DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, DSC_IDX);
> +	DPU_REG_WRITE(c, CTL_DSC_ACTIVE, cfg->dsc);
>  }
>  
>  static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx,
> -- 
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>