[PATCH v2 0/5] MDSS reg bus interconnect
Konrad Dybcio
konrad.dybcio at linaro.org
Tue Apr 18 12:10:55 UTC 2023
v1 -> v2:
- Fix "Mbps" -> "MBps" [5/5]
- Add an interconnects: entry in dt-bindings (and not only -names..) [1/5]
v1: https://lore.kernel.org/r/20230417-topic-dpu_regbus-v1-0-06fbdc1643c0@linaro.org
Apart from the already handled data bus (MAS_MDP_Pn<->DDR), there's
another path that needs to be handled to ensure MDSS functions properly,
namely the "reg bus", a.k.a the CPU-MDSS interconnect.
Gating that path may have a variety of effects.. from none to otherwise
inexplicable DSI timeouts..
This series tries to address the lack of that.
Example path:
interconnects = <&bimc MASTER_AMPSS_M0 0 &config_noc SLAVE_DISPLAY_CFG 0>;
Signed-off-by: Konrad Dybcio <konrad.dybcio at linaro.org>
---
Konrad Dybcio (5):
dt-bindings: display/msm: Add reg bus interconnect
drm/msm/dpu1: Rename path references to mdp_path
drm/msm/mdss: Rename path references to mdp_path
drm/msm/mdss: Handle the reg bus ICC path
drm/msm/dpu1: Handle the reg bus ICC path
.../bindings/display/msm/mdss-common.yaml | 2 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 10 +++----
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 34 ++++++++++++++++-----
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 5 ++--
drivers/gpu/drm/msm/msm_mdss.c | 35 ++++++++++++++--------
5 files changed, 58 insertions(+), 28 deletions(-)
---
base-commit: 4aa1da8d99724f6c0b762b58a71cee7c5e2e109b
change-id: 20230417-topic-dpu_regbus-abc94a770952
Best regards,
--
Konrad Dybcio <konrad.dybcio at linaro.org>
More information about the dri-devel
mailing list