[PATCH V2 5/6] drm: bridge: samsung-dsim: Support non-burst mode

[Marek Szyprowski]

On 23.04.2023 14:12, Adam Ford wrote:
> The high-speed clock is hard-coded to the burst-clock
> frequency specified in the device tree.  However, when
> using devices like certain bridge chips without burst mode
> and varying resolutions and refresh rates, it may be
> necessary to set the high-speed clock dynamically based
> on the desired pixel clock for the connected device.
>
> This also removes the need to set a clock speed from
> the device tree for non-burst mode operation, since the
> pixel clock rate is the rate requested from the attached
> device like an HDMI bridge chip.  This should have no
> impact for people using burst-mode and setting the burst
> clock rate is still required for those users.
>
> Signed-off-by: Adam Ford <aford173 at gmail.com>

This one breaks Exynos-5433 based TM2e board with a DSI panel.

> ---
>   drivers/gpu/drm/bridge/samsung-dsim.c | 17 ++++++++++++++---
>   1 file changed, 14 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c
> index f165483d5044..cea847b8e23c 100644
> --- a/drivers/gpu/drm/bridge/samsung-dsim.c
> +++ b/drivers/gpu/drm/bridge/samsung-dsim.c
> @@ -657,11 +657,21 @@ static unsigned long samsung_dsim_set_pll(struct samsung_dsim *dsi,
>   
>   static int samsung_dsim_enable_clock(struct samsung_dsim *dsi)
>   {
> -	unsigned long hs_clk, byte_clk, esc_clk;
> +	unsigned long hs_clk, byte_clk, esc_clk, pix_clk;
>   	unsigned long esc_div;
>   	u32 reg;
> +	struct drm_display_mode *m = &dsi->mode;
> +	int bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
> +
> +	/* m->clock is in KHz */
> +	pix_clk = m->clock * 1000;
> +
> +	/* Use burst_clk_rate for burst mode, otherwise use the pix_clk */
> +	if ((dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) && dsi->burst_clk_rate)
> +		hs_clk = samsung_dsim_set_pll(dsi, dsi->burst_clk_rate);
> +	else
> +		hs_clk = samsung_dsim_set_pll(dsi, DIV_ROUND_UP(pix_clk * bpp, dsi->lanes));
>   
> -	hs_clk = samsung_dsim_set_pll(dsi, dsi->burst_clk_rate);
>   	if (!hs_clk) {
>   		dev_err(dsi->dev, "failed to configure DSI PLL\n");
>   		return -EFAULT;
> @@ -1800,10 +1810,11 @@ static int samsung_dsim_parse_dt(struct samsung_dsim *dsi)
>   			return PTR_ERR(pll_clk);
>   	}
>   
> +	/* If it doesn't exist, use pixel clock instead of failing */
>   	ret = samsung_dsim_of_read_u32(node, "samsung,burst-clock-frequency",
>   				       &dsi->burst_clk_rate);
>   	if (ret < 0)
> -		return ret;
> +		dsi->burst_clk_rate = 0;
>   
>   	ret = samsung_dsim_of_read_u32(node, "samsung,esc-clock-frequency",
>   				       &dsi->esc_clk_rate);

Best regards
-- 
Marek Szyprowski, PhD
Samsung R&D Institute Poland