[bug report] drm/imagination: Implement firmware infrastructure and META FW support

[Dan Carpenter]

Hello Sarah Walker,

The patch cc1aeedb98ad: "drm/imagination: Implement firmware
infrastructure and META FW support" from Nov 22, 2023 (linux-next),
leads to the following Smatch static checker warning:

drivers/gpu/drm/imagination/pvr_fw_startstop.c:210 pvr_fw_stop() warn: odd mask '0xffff & 0xffff0000'
drivers/gpu/drm/imagination/pvr_fw_startstop.c:213 pvr_fw_stop() warn: odd mask '0xffff & 0xffff0000'
drivers/gpu/drm/imagination/pvr_fw_startstop.c:216 pvr_fw_stop() warn: odd mask '0xffff & 0xffff0000'
drivers/gpu/drm/imagination/pvr_fw_startstop.c:219 pvr_fw_stop() warn: odd mask '0xffff & 0xffff0000'

drivers/gpu/drm/imagination/pvr_fw_startstop.c
    187 int
    188 pvr_fw_stop(struct pvr_device *pvr_dev)
    189 {
    190         const u32 sidekick_idle_mask = ROGUE_CR_SIDEKICK_IDLE_MASKFULL &
    191                                        ~(ROGUE_CR_SIDEKICK_IDLE_GARTEN_EN |
    192                                          ROGUE_CR_SIDEKICK_IDLE_SOCIF_EN |
    193                                          ROGUE_CR_SIDEKICK_IDLE_HOSTIF_EN);
    194         bool skip_garten_idle = false;
    195         u32 reg_value;
    196         int err;
    197 
    198         /*
    199          * Wait for Sidekick/Jones to signal IDLE except for the Garten Wrapper.
    200          * For cores with the LAYOUT_MARS feature, SIDEKICK would have been
    201          * powered down by the FW.
    202          */
    203         err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SIDEKICK_IDLE, sidekick_idle_mask,
    204                                 sidekick_idle_mask, POLL_TIMEOUT_USEC);
    205         if (err)
    206                 return err;
    207 
    208         /* Unset MTS DM association with threads. */
    209         pvr_cr_write32(pvr_dev, ROGUE_CR_MTS_INTCTX_THREAD0_DM_ASSOC,
--> 210                        ROGUE_CR_MTS_INTCTX_THREAD0_DM_ASSOC_MASKFULL &
    211                        ROGUE_CR_MTS_INTCTX_THREAD0_DM_ASSOC_DM_ASSOC_CLRMSK);

What's the point of these masks?  They don't overlap so they just equal
zero.

    212         pvr_cr_write32(pvr_dev, ROGUE_CR_MTS_BGCTX_THREAD0_DM_ASSOC,
    213                        ROGUE_CR_MTS_BGCTX_THREAD0_DM_ASSOC_MASKFULL &
    214                        ROGUE_CR_MTS_BGCTX_THREAD0_DM_ASSOC_DM_ASSOC_CLRMSK);
    215         pvr_cr_write32(pvr_dev, ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC,
    216                        ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC_MASKFULL &
    217                        ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC_DM_ASSOC_CLRMSK);
    218         pvr_cr_write32(pvr_dev, ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC,
    219                        ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC_MASKFULL &
    220                        ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC_DM_ASSOC_CLRMSK);
    221 
    222         /* Extra Idle checks. */
    223         err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_BIF_STATUS_MMU, 0,

regards,
dan carpenter