[PATCH 1/3] drm/panel: st7701: Fix AVCL calculation

Linus Walleij linus.walleij at linaro.org
Mon Dec 11 23:43:47 UTC 2023


On Fri, Dec 8, 2023 at 4:48 PM Chris Morgan <macroalpha82 at gmail.com> wrote:

> From: Chris Morgan <macromorgan at hotmail.com>
>
> The AVCL register, according to the datasheet, comes in increments
> of -0.2v between -4.4v (represented by 0x0) to -5.0v (represented
> by 0x3). The current calculation is done by adding the defined
> AVCL value in mV to -4400 and then dividing by 200 to get the register
> value. Unfortunately if I subtract -4400 from -4400 I get -8800, which
> divided by 200 gives me -44. If I instead subtract -4400 from -4400
> I get 0, which divided by 200 gives me 0. Based on the datasheet this
> is the expected register value.
>
> Fixes: 83b7a8e7e88e ("drm/panel/panel-sitronix-st7701: Parametrize voltage and timing")
>
> Signed-off-by: Chris Morgan <macromorgan at hotmail.com>

Good catch!

Reviewed-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


More information about the dri-devel mailing list