[PATCH v15 3/5] drm: renesas: Add RZ/G2L DU Support

[Biju Das]

Hi Maxime Ripard,

> -----Original Message-----
> From: Maxime Ripard <mripard at kernel.org>
> Sent: Friday, December 15, 2023 10:24 AM
> Subject: Re: [PATCH v15 3/5] drm: renesas: Add RZ/G2L DU Support
> 
> On Thu, Dec 14, 2023 at 03:24:17PM +0000, Biju Das wrote:
> > Hi Maxime Ripard,
> >
> > Thanks for the feedback.
> 
> Thanks, that's super helpful. The architecture is thus similar to vc4
> 
> Some general questions related to bugs we had at some point with vc4:
> 
>   * Where is the display list stored? In RAM or in a dedicated SRAM?

[1] It is in DDR (RAM).

> 
>   * Are the pointer to the current display list latched?
> 
>   * Is the display list itself latched? If it's not, what happens when
>     the display list is changed while the frame is being generated?

There is some protocol defined for SW side and HW side for updating display list
See [1] 33.4.8.1 Operation flow of VSPD and DU.

All the display list operations are manged here[2]

[1] https://www.renesas.com/us/en/document/mah/rzg2l-group-rzg2lc-group-users-manual-hardware-0

[2] https://elixir.bootlin.com/linux/v6.7-rc5/source/drivers/media/platform/renesas/vsp1/vsp1_dl.c#L863

Cheers,
Biju