[PATCH 2/2] drm/mediatek: Add support for AR30 and BA30 overlays

[Chun-Kuang Hu]

Hi, Justin:

Justin Green <greenjustin at chromium.org> 於 2023年2月1日 週三 上午4:09寫道：
>
> Add support for overlays with pixel formats AR30 and BA30 on MT8195.

I would like to break this patch into two patches. One is ovl support
AR30 and BA30, and the other one is mt8195 ovl support AR30 and BA30.

>
> Tested using "modetest -P" on an MT8195 device.
>
> Signed-off-by: Justin Green <greenjustin at chromium.org>
> ---
>  drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 49 ++++++++++++++++++++++++-
>  1 file changed, 47 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> index 8743c8047dc9..cd2f9a156456 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> @@ -41,6 +41,7 @@
>  #define DISP_REG_OVL_RDMA_CTRL(n)              (0x00c0 + 0x20 * (n))
>  #define DISP_REG_OVL_RDMA_GMC(n)               (0x00c8 + 0x20 * (n))
>  #define DISP_REG_OVL_ADDR_MT2701               0x0040
> +#define DISP_REG_OVL_CLRFMT_EXT                        0x02D0
>  #define DISP_REG_OVL_ADDR_MT8173               0x0f40
>  #define DISP_REG_OVL_ADDR(ovl, n)              ((ovl)->data->addr + 0x20 * (n))
>  #define DISP_REG_OVL_HDR_ADDR(ovl, n)          ((ovl)->data->addr + 0x20 * (n) + 0x04)
> @@ -61,6 +62,10 @@
>                                         0 : OVL_CON_CLRFMT_RGB)
>  #define OVL_CON_CLRFMT_RGB888(ovl)     ((ovl)->data->fmt_rgb565_is_0 ? \
>                                         OVL_CON_CLRFMT_RGB : 0)
> +#define OVL_CON_CLRFMT_BIT_DEPTH_MASK(ovl)     (0xFF << 4 * (ovl))
> +#define OVL_CON_CLRFMT_BIT_DEPTH(depth, ovl)   (depth << 4 * (ovl))
> +#define OVL_CON_CLRFMT_8_BIT                   0x00
> +#define OVL_CON_CLRFMT_10_BIT                  0x01
>  #define        OVL_CON_AEN             BIT(8)
>  #define        OVL_CON_ALPHA           0xff
>  #define        OVL_CON_VIRT_FLIP       BIT(9)
> @@ -80,6 +85,22 @@ static const u32 mt8173_formats[] = {
>         DRM_FORMAT_YUYV,
>  };
>
> +static const u32 mt8195_formats[] = {
> +       DRM_FORMAT_XRGB8888,
> +       DRM_FORMAT_ARGB8888,
> +       DRM_FORMAT_ARGB2101010,
> +       DRM_FORMAT_BGRX8888,
> +       DRM_FORMAT_BGRA8888,
> +       DRM_FORMAT_BGRA1010102,
> +       DRM_FORMAT_ABGR8888,
> +       DRM_FORMAT_XBGR8888,
> +       DRM_FORMAT_RGB888,
> +       DRM_FORMAT_BGR888,
> +       DRM_FORMAT_RGB565,
> +       DRM_FORMAT_UYVY,
> +       DRM_FORMAT_YUYV,
> +};
> +
>  struct mtk_disp_ovl_data {
>         unsigned int addr;
>         unsigned int gmc_bits;
> @@ -218,6 +239,27 @@ static void mtk_ovl_set_afbc(struct mtk_disp_ovl *ovl, struct cmdq_pkt *cmdq_pkt
>                            DISP_REG_OVL_DATAPATH_CON, OVL_LAYER_AFBC_EN(idx));
>  }
>
> +static void mtk_ovl_set_bit_depth(struct device *dev, int idx, u32 format,
> +                                 struct cmdq_pkt *cmdq_pkt)
> +{
> +       struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
> +       unsigned int reg;
> +       unsigned int bit_depth = OVL_CON_CLRFMT_8_BIT;
> +
> +       reg = readl(ovl->regs + DISP_REG_OVL_CLRFMT_EXT);
> +       reg &= ~OVL_CON_CLRFMT_BIT_DEPTH_MASK(idx);
> +
> +       if (format == DRM_FORMAT_RGBA1010102 ||
> +           format == DRM_FORMAT_BGRA1010102 ||
> +           format == DRM_FORMAT_ARGB2101010)
> +               bit_depth = OVL_CON_CLRFMT_10_BIT;
> +
> +       reg |= OVL_CON_CLRFMT_BIT_DEPTH(bit_depth, idx);
> +
> +       mtk_ddp_write(cmdq_pkt, reg, &ovl->cmdq_reg,
> +                     ovl->regs, DISP_REG_OVL_CLRFMT_EXT);

Does all SoC have this register? If no, you should write this register
for the SoC have this register.

Regards,
Chun-Kuang.

> +}
> +
>  void mtk_ovl_config(struct device *dev, unsigned int w,
>                     unsigned int h, unsigned int vrefresh,
>                     unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> @@ -332,9 +374,11 @@ static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt)
>                 return OVL_CON_CLRFMT_ARGB8888;
>         case DRM_FORMAT_BGRX8888:
>         case DRM_FORMAT_BGRA8888:
> +       case DRM_FORMAT_BGRA1010102:
>                 return OVL_CON_CLRFMT_ARGB8888 | OVL_CON_BYTE_SWAP;
>         case DRM_FORMAT_XRGB8888:
>         case DRM_FORMAT_ARGB8888:
> +       case DRM_FORMAT_ARGB2101010:
>                 return OVL_CON_CLRFMT_RGBA8888;
>         case DRM_FORMAT_XBGR8888:
>         case DRM_FORMAT_ABGR8888:
> @@ -418,6 +462,7 @@ void mtk_ovl_layer_config(struct device *dev, unsigned int idx,
>                                       &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_PITCH_MSB(idx));
>         }
>
> +       mtk_ovl_set_bit_depth(dev, idx, fmt, cmdq_pkt);
>         mtk_ovl_layer_on(dev, idx, cmdq_pkt);
>  }
>
> @@ -583,8 +628,8 @@ static const struct mtk_disp_ovl_data mt8195_ovl_driver_data = {
>         .fmt_rgb565_is_0 = true,
>         .smi_id_en = true,
>         .supports_afbc = true,
> -       .formats = mt8173_formats,
> -       .num_formats = ARRAY_SIZE(mt8173_formats),
> +       .formats = mt8195_formats,
> +       .num_formats = ARRAY_SIZE(mt8195_formats),
>  };
>
>  static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = {
> --
> 2.39.1.456.gfc5497dd1b-goog
>