[PATCH v2 00/14] GMU-less A6xx support (A610, A619_holi)

[Rob Clark]

+ Akhil

On Tue, Feb 14, 2023 at 10:03 AM Konrad Dybcio <konrad.dybcio at linaro.org> wrote:
>
>
> v1 -> v2:
> - Fix A630 values in [2/14]
> - Fix [6/14] for GMU-equipped GPUs
>
> Link to v1: https://lore.kernel.org/linux-arm-msm/20230126151618.225127-1-konrad.dybcio@linaro.org/
>
> This series concludes my couple-weeks-long suffering of figuring out
> the ins and outs of the "non-standard" A6xx GPUs which feature no GMU.
>
> The GMU functionality is essentially emulated by parting out a
> "GMU wrapper" region, which is essentially just a register space
> within the GPU. It's modeled to be as similar to the actual GMU
> as possible while staying as unnecessary as we can make it - there's
> no IRQs, communicating with a microcontroller, no RPMh communication
> etc. etc. I tried to reuse as much code as possible without making
> a mess where every even line is used for GMU and every odd line is
> used for GMU wrapper..
>
> This series contains:
> - plumbing for non-GMU operation, if-ing out GMU calls based on
>   GMU presence
> - GMU wrapper support
> - A610 support (w/ speedbin)
> - A619 support (w/ speedbin)
> - couple of minor fixes and improvements
> - VDDCX/VDDGX scaling fix for non-GMU GPUs (concerns more than just
>   A6xx)
> - Enablement of opp interconnect properties
>
> A619_holi works perfectly fine using the already-present A619 support
> in mesa. A610 needs more work on that front, but can already replay
> command traces captures on downstream.
>
> NOTE: the "drm/msm/a6xx: Add support for A619_holi" patch contains
> two occurences of 0x18 used in place of a register #define, as it's
> supposed to be RBBM_GPR0_CNTL, but that will only be present after
> mesa-side changes are merged and headers are synced from there.
>
> Speedbin patches depend on:
> https://lore.kernel.org/linux-arm-msm/20230120172233.1905761-1-konrad.dybcio@linaro.org/
>
>
> Konrad Dybcio (14):
>   drm/msm/a6xx: De-staticize sptprac en/disable functions
>   drm/msm/a6xx: Extend UBWC config
>   drm/msm/a6xx: Introduce GMU wrapper support
>   drm/msm/a6xx: Remove both GBIF and RBBM GBIF halt on hw init
>   drm/msm/adreno: Disable has_cached_coherent for A610/A619_holi
>   drm/msm/gpu: Use dev_pm_opp_set_rate for non-GMU GPUs
>   drm/msm/a6xx: Add support for A619_holi
>   drm/msm/a6xx: Add A610 support
>   drm/msm/a6xx: Fix some A619 tunables
>   drm/msm/a6xx: Fix up A6XX protected registers
>   drm/msm/a6xx: Enable optional icc voting from OPP tables
>   drm/msm/a6xx: Use "else if" in GPU speedbin rev matching
>   drm/msm/a6xx: Add A619_holi speedbin support
>   drm/msm/a6xx: Add A610 speedbin support
>
>  drivers/gpu/drm/msm/adreno/a6xx_gmu.c       |  55 ++-
>  drivers/gpu/drm/msm/adreno/a6xx_gmu.h       |   2 +
>  drivers/gpu/drm/msm/adreno/a6xx_gpu.c       | 427 +++++++++++++++++---
>  drivers/gpu/drm/msm/adreno/a6xx_gpu.h       |   1 +
>  drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c |  14 +-
>  drivers/gpu/drm/msm/adreno/adreno_device.c  |  34 +-
>  drivers/gpu/drm/msm/adreno/adreno_gpu.c     |   4 +
>  drivers/gpu/drm/msm/adreno/adreno_gpu.h     |  19 +-
>  drivers/gpu/drm/msm/msm_gpu_devfreq.c       |   2 +-
>  9 files changed, 492 insertions(+), 66 deletions(-)
>
> --
> 2.39.1
>