[PATCH v5] drm/i915: Consolidate TLB invalidation flow

[Tvrtko Ursulin]

On 16/02/2023 15:41, Matt Roper wrote:
> On Thu, Feb 16, 2023 at 09:21:23AM +0000, Tvrtko Ursulin wrote:
>> From: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
>>
>> As the logic for selecting the register and corresponsing values grew, the
>> code become a bit unsightly. Consolidate by storing the required values at
>> engine init time in the engine itself, and by doing so minimise the amount
>> of invariant platform and engine checks during each and every TLB
>> invalidation.
>>
>> v2:
>>   * Fail engine probe if TLB invlidations registers are unknown.
>>
>> v3:
>>   * Rebase.
>>
>> v4:
>>   * Fix handling of GEN8_M2TCR. (Andrzej)
>>
>> v5:
>>   * Tidy checkpatch warnings.
>>
>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
>> Cc: Andrzej Hajda <andrzej.hajda at intel.com>
>> Cc: Matt Roper <matthew.d.roper at intel.com>
>> Reviewed-by: Andrzej Hajda <andrzej.hajda at intel.com> # v1
>> Reviewed-by: Matt Roper <matthew.d.roper at intel.com> # v3
> 
> Reviewed-by: Matt Roper <matthew.d.roper at intel.com>
> 
> for this version as well.

Thanks Matt, pushed.

Regards,

Tvrtko