[PATCH v4] drm/i915: Do not cover all future platforms in TLB invalidation

[Tvrtko Ursulin]

On 10/01/2023 16:07, Matt Roper wrote:
> On Tue, Jan 10, 2023 at 11:35:33AM +0000, Tvrtko Ursulin wrote:
>> From: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
>>
>> Revert to the original explicit approach and document the reasoning
>> behind it.
>>
>> v2:
>>   * DG2 needs to be covered too. (Matt)
>>
>> v3:
>>   * Full version check for Gen12 to avoid catching all future platforms.
>>     (Matt)
>>
>> v4:
>>   * Be totally explicit on the Gen12 branch. (Andrzej)
>>
>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
>> Cc: Matt Roper <matthew.d.roper at intel.com>
>> Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan at intel.com>
>> Cc: Andrzej Hajda <andrzej.hajda at intel.com>
>> Reviewed-by: Andrzej Hajda <andrzej.hajda at intel.com> # v1
>> Reviewed-by: Matt Roper <matthew.d.roper at intel.com> # v3
> 
> Reviewed-by: Matt Roper <matthew.d.roper at intel.com>
> 
> for v4 as well.

Thanks, pushed!

So next I have that patch which moves the register/bits selection logic 
to engine init time. I will send it out rebased but do not intend to 
merge before the tlb invalidation selftest can land upstream.

Regards,

Tvrtko