[PATCH 1/3] drm/msm/dpu: handle UBWC 1.0 in dpu_hw_sspp_setup_format

[Abhinav Kumar]

On 12/7/2022 6:28 AM, Dmitry Baryshkov wrote:
> Extend dpu_hw_sspp_setup_format() to also handle the UBWC 1.0 case.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov at linaro.org>

Reviewed-by: Abhinav Kumar <quic_abhinavk at quicinc.com>

> ---
>   drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 6 +++++-
>   1 file changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> index 691c471b08c2..4246ab0b3bee 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> @@ -310,7 +310,11 @@ static void dpu_hw_sspp_setup_format(struct dpu_hw_pipe *ctx,
>   			ctx->mdp->highest_bank_bit << 18);
>   		switch (ctx->catalog->caps->ubwc_version) {
>   		case DPU_HW_UBWC_VER_10:
> -			/* TODO: UBWC v1 case */
> +			fast_clear = fmt->alpha_enable ? BIT(31) : 0;
> +			DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
> +					fast_clear | (ctx->mdp->ubwc_swizzle & 0x1) |
> +					BIT(8) |
> +					(ctx->mdp->highest_bank_bit << 4));
>   			break;
>   		case DPU_HW_UBWC_VER_20:
>   			fast_clear = fmt->alpha_enable ? BIT(31) : 0;