[PATCH v3 2/8] drm/i915/pxp: Add MTL hw-plumbing enabling for KCR operation
Ceraolo Spurio, Daniele
daniele.ceraolospurio at intel.com
Fri Jan 27 00:20:19 UTC 2023
On 1/25/2023 12:06 AM, Alan Previn wrote:
> Add MTL hw-plumbing enabling for KCR operation under PXP
> which includes:
>
> 1. Updating 'pick-gt' to get the media tile for
> KCR interrupt handling
> 2. Adding MTL's KCR registers for PXP operation
> (init, status-checking, etc.).
>
> While doing #2, lets create a separate registers header file for PXP
> to be consistent with other i915 global subsystems.
>
> Signed-off-by: Alan Previn <alan.previn.teres.alexis at intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com>
Daniele
> ---
> drivers/gpu/drm/i915/gt/intel_gt_irq.c | 3 +-
> drivers/gpu/drm/i915/pxp/intel_pxp.c | 32 ++++++++++++--------
> drivers/gpu/drm/i915/pxp/intel_pxp_regs.h | 27 +++++++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 12 +++-----
> drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 6 ++++
> 5 files changed, 58 insertions(+), 22 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_regs.h
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> index 1b25a6039152..c360776a98b5 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> @@ -100,7 +100,8 @@ static struct intel_gt *pick_gt(struct intel_gt *gt, u8 class, u8 instance)
> case VIDEO_ENHANCEMENT_CLASS:
> return media_gt;
> case OTHER_CLASS:
> - if (instance == OTHER_GSC_INSTANCE && HAS_ENGINE(media_gt, GSC0))
> + if ((instance == OTHER_GSC_INSTANCE || instance == OTHER_KCR_INSTANCE) &&
> + HAS_ENGINE(media_gt, GSC0))
> return media_gt;
> fallthrough;
> default:
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> index 22280408156e..4350921e40c4 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -14,6 +14,7 @@
> #include "intel_pxp.h"
> #include "intel_pxp_gsccs.h"
> #include "intel_pxp_irq.h"
> +#include "intel_pxp_regs.h"
> #include "intel_pxp_session.h"
> #include "intel_pxp_tee.h"
> #include "intel_pxp_types.h"
> @@ -61,21 +62,22 @@ bool intel_pxp_is_active(const struct intel_pxp *pxp)
> return IS_ENABLED(CONFIG_DRM_I915_PXP) && pxp && pxp->arb_is_valid;
> }
>
> -/* KCR register definitions */
> -#define KCR_INIT _MMIO(0x320f0)
> -/* Setting KCR Init bit is required after system boot */
> -#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES REG_BIT(14)
> +static void kcr_pxp_set_status(const struct intel_pxp *pxp, bool enable)
> +{
> + u32 val = enable ? _MASKED_BIT_ENABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES) :
> + _MASKED_BIT_DISABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES);
> +
> + intel_uncore_write(pxp->ctrl_gt->uncore, KCR_INIT(pxp->kcr_base), val);
> +}
>
> -static void kcr_pxp_enable(struct intel_gt *gt)
> +static void kcr_pxp_enable(const struct intel_pxp *pxp)
> {
> - intel_uncore_write(gt->uncore, KCR_INIT,
> - _MASKED_BIT_ENABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES));
> + kcr_pxp_set_status(pxp, true);
> }
>
> -static void kcr_pxp_disable(struct intel_gt *gt)
> +static void kcr_pxp_disable(const struct intel_pxp *pxp)
> {
> - intel_uncore_write(gt->uncore, KCR_INIT,
> - _MASKED_BIT_DISABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES));
> + kcr_pxp_set_status(pxp, false);
> }
>
> static int create_vcs_context(struct intel_pxp *pxp)
> @@ -127,6 +129,11 @@ static void pxp_init_full(struct intel_pxp *pxp)
> init_completion(&pxp->termination);
> complete_all(&pxp->termination);
>
> + if (pxp->ctrl_gt->type == GT_MEDIA)
> + pxp->kcr_base = MTL_KCR_BASE;
> + else
> + pxp->kcr_base = GEN12_KCR_BASE;
> +
> intel_pxp_session_management_init(pxp);
>
> ret = create_vcs_context(pxp);
> @@ -319,14 +326,13 @@ int intel_pxp_start(struct intel_pxp *pxp)
>
> void intel_pxp_init_hw(struct intel_pxp *pxp)
> {
> - kcr_pxp_enable(pxp->ctrl_gt);
> + kcr_pxp_enable(pxp);
> intel_pxp_irq_enable(pxp);
> }
>
> void intel_pxp_fini_hw(struct intel_pxp *pxp)
> {
> - kcr_pxp_disable(pxp->ctrl_gt);
> -
> + kcr_pxp_disable(pxp);
> intel_pxp_irq_disable(pxp);
> }
>
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_regs.h b/drivers/gpu/drm/i915/pxp/intel_pxp_regs.h
> new file mode 100644
> index 000000000000..a9e7e6efa4c7
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_regs.h
> @@ -0,0 +1,27 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright(c) 2023, Intel Corporation. All rights reserved.
> + */
> +
> +#ifndef __INTEL_PXP_REGS_H__
> +#define __INTEL_PXP_REGS_H__
> +
> +#include "i915_reg_defs.h"
> +
> +/* KCR subsystem register base address */
> +#define GEN12_KCR_BASE 0x32000
> +#define MTL_KCR_BASE 0x386000
> +
> +/* KCR enable/disable control */
> +#define KCR_INIT(base) _MMIO((base) + 0xf0)
> +
> +/* Setting KCR Init bit is required after system boot */
> +#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES REG_BIT(14)
> +
> +/* KCR hwdrm session in play status 0-31 */
> +#define KCR_SIP(base) _MMIO((base) + 0x260)
> +
> +/* PXP global terminate register for session termination */
> +#define KCR_GLOBAL_TERMINATE(base) _MMIO((base) + 0xf8)
> +
> +#endif /* __INTEL_PXP_REGS_H__ */
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
> index ae413580b81a..28f5ca838cb7 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
> @@ -10,14 +10,10 @@
> #include "intel_pxp_session.h"
> #include "intel_pxp_tee.h"
> #include "intel_pxp_types.h"
> +#include "intel_pxp_regs.h"
>
> #define ARB_SESSION I915_PROTECTED_CONTENT_DEFAULT_SESSION /* shorter define */
>
> -#define GEN12_KCR_SIP _MMIO(0x32260) /* KCR hwdrm session in play 0-31 */
> -
> -/* PXP global terminate register for session termination */
> -#define PXP_GLOBAL_TERMINATE _MMIO(0x320f8)
> -
> static bool intel_pxp_session_is_in_play(struct intel_pxp *pxp, u32 id)
> {
> struct intel_uncore *uncore = pxp->ctrl_gt->uncore;
> @@ -26,7 +22,7 @@ static bool intel_pxp_session_is_in_play(struct intel_pxp *pxp, u32 id)
>
> /* if we're suspended the session is considered off */
> with_intel_runtime_pm_if_in_use(uncore->rpm, wakeref)
> - sip = intel_uncore_read(uncore, GEN12_KCR_SIP);
> + sip = intel_uncore_read(uncore, KCR_SIP(pxp->kcr_base));
>
> return sip & BIT(id);
> }
> @@ -44,7 +40,7 @@ static int pxp_wait_for_session_state(struct intel_pxp *pxp, u32 id, bool in_pla
> return in_play ? -ENODEV : 0;
>
> ret = intel_wait_for_register(uncore,
> - GEN12_KCR_SIP,
> + KCR_SIP(pxp->kcr_base),
> mask,
> in_play ? mask : 0,
> 100);
> @@ -108,7 +104,7 @@ static int pxp_terminate_arb_session_and_global(struct intel_pxp *pxp)
> return ret;
> }
>
> - intel_uncore_write(gt->uncore, PXP_GLOBAL_TERMINATE, 1);
> + intel_uncore_write(gt->uncore, KCR_GLOBAL_TERMINATE(pxp->kcr_base), 1);
>
> return ret;
> }
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
> index 326bd8414407..be51e43ac23d 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
> @@ -26,6 +26,12 @@ struct intel_pxp {
> */
> struct intel_gt *ctrl_gt;
>
> + /**
> + * @kcr_base: base mmio offset for the KCR engine which is different on legacy platforms
> + * vs newer platforms where the KCR is inside the media-tile.
> + */
> + u32 kcr_base;
> +
> /**
> * @gsccs_res: resources for request submission for platforms that have a GSC engine.
> */
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