[PATCH v2] drm/mediatek: Add support for AR30 and BA30
Chun-Kuang Hu
chunkuang.hu at kernel.org
Fri Jan 27 00:36:13 UTC 2023
Hi, Justin:
Justin Green <greenjustin at chromium.org> 於 2023年1月11日 週三 上午4:47寫道：
>
> Add support for AR30 and BA30 pixel formats to the Mediatek DRM driver.
>
> Tested using "modetest -P" on an MT8195.
>
> Signed-off-by: Justin Green <greenjustin at chromium.org>
> ---
> v2:
> * Rebase and resolve merge conflicts with the AFBC patch.
>
> drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 28 +++++++++++++++++
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 19 +++++++++++-
> drivers/gpu/drm/mediatek/mtk_drm_plane.c | 39 +++++++++++++++++++++---
> drivers/gpu/drm/mediatek/mtk_drm_plane.h | 2 +-
> 4 files changed, 81 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> index 84daeaffab6a..667ae57c8754 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> @@ -41,6 +41,7 @@
> #define DISP_REG_OVL_RDMA_CTRL(n) (0x00c0 + 0x20 * (n))
> #define DISP_REG_OVL_RDMA_GMC(n) (0x00c8 + 0x20 * (n))
> #define DISP_REG_OVL_ADDR_MT2701 0x0040
> +#define DISP_REG_OVL_CLRFMT_EXT 0x02D0
> #define DISP_REG_OVL_ADDR_MT8173 0x0f40
> #define DISP_REG_OVL_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n))
> #define DISP_REG_OVL_HDR_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n) + 0x04)
> @@ -61,6 +62,10 @@
> 0 : OVL_CON_CLRFMT_RGB)
> #define OVL_CON_CLRFMT_RGB888(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \
> OVL_CON_CLRFMT_RGB : 0)
> +#define OVL_CON_CLRFMT_BIT_DEPTH_MASK(ovl) (0xFF << 4 * (ovl))
> +#define OVL_CON_CLRFMT_BIT_DEPTH(depth, ovl) (depth << 4 * (ovl))
> +#define OVL_CON_CLRFMT_8_BIT 0x00
> +#define OVL_CON_CLRFMT_10_BIT 0x01
> #define OVL_CON_AEN BIT(8)
> #define OVL_CON_ALPHA 0xff
> #define OVL_CON_VIRT_FLIP BIT(9)
> @@ -188,6 +193,26 @@ static void mtk_ovl_set_afbc(struct mtk_disp_ovl *ovl, struct cmdq_pkt *cmdq_pkt
> DISP_REG_OVL_DATAPATH_CON, OVL_LAYER_AFBC_EN(idx));
> }
>
> +static void mtk_ovl_set_bit_depth(struct device *dev, int idx, u32 format,
> + struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
> + unsigned int reg;
> + unsigned int bit_depth = OVL_CON_CLRFMT_8_BIT;
> +
> + reg = readl(ovl->regs + DISP_REG_OVL_CLRFMT_EXT);
> + reg &= ~OVL_CON_CLRFMT_BIT_DEPTH_MASK(idx);
> +
> + if (format == DRM_FORMAT_RGBA1010102 ||
> + format == DRM_FORMAT_BGRA1010102 ||
> + format == DRM_FORMAT_ARGB2101010)
> + bit_depth = OVL_CON_CLRFMT_10_BIT;
> +
> + reg |= OVL_CON_CLRFMT_BIT_DEPTH(bit_depth, idx);
> +
> + mtk_ddp_write(cmdq_pkt, reg, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_CLRFMT_EXT);
> +}
> +
> void mtk_ovl_config(struct device *dev, unsigned int w,
> unsigned int h, unsigned int vrefresh,
> unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> @@ -302,9 +327,11 @@ static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt)
> return OVL_CON_CLRFMT_ARGB8888;
> case DRM_FORMAT_BGRX8888:
> case DRM_FORMAT_BGRA8888:
> + case DRM_FORMAT_BGRA1010102:
> return OVL_CON_CLRFMT_ARGB8888 | OVL_CON_BYTE_SWAP;
> case DRM_FORMAT_XRGB8888:
> case DRM_FORMAT_ARGB8888:
> + case DRM_FORMAT_ARGB2101010:
> return OVL_CON_CLRFMT_RGBA8888;
> case DRM_FORMAT_XBGR8888:
> case DRM_FORMAT_ABGR8888:
> @@ -388,6 +415,7 @@ void mtk_ovl_layer_config(struct device *dev, unsigned int idx,
> &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_PITCH_MSB(idx));
> }
>
> + mtk_ovl_set_bit_depth(dev, idx, fmt, cmdq_pkt);
> mtk_ovl_layer_on(dev, idx, cmdq_pkt);
> }
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> index 112615817dcb..d50379c97c4b 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> @@ -842,6 +842,21 @@ enum drm_plane_type mtk_drm_crtc_plane_type(unsigned int plane_idx,
>
> }
>
> +static const char *ovls_with_10bit_cap[] = {
> + "mediatek,mt8195-disp-ovl",
> +};
> +
> +static bool is_10bit_cap_device(void)
> +{
> + for (int i = 0; i < ARRAY_SIZE(ovls_with_10bit_cap); i++) {
> + if (of_find_compatible_node(NULL, NULL,
> + ovls_with_10bit_cap[i]))
> + return true;
> + }
> +
> + return false;
> +}
> +
> static int mtk_drm_crtc_init_comp_planes(struct drm_device *drm_dev,
> struct mtk_drm_crtc *mtk_crtc,
> int comp_idx, int pipe)
> @@ -849,6 +864,7 @@ static int mtk_drm_crtc_init_comp_planes(struct drm_device *drm_dev,
> int num_planes = mtk_drm_crtc_num_comp_planes(mtk_crtc, comp_idx);
> struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[comp_idx];
> int i, ret;
> + bool supports_10bit = is_10bit_cap_device();
>
> for (i = 0; i < num_planes; i++) {
> ret = mtk_plane_init(drm_dev,
> @@ -856,7 +872,8 @@ static int mtk_drm_crtc_init_comp_planes(struct drm_device *drm_dev,
> BIT(pipe),
> mtk_drm_crtc_plane_type(mtk_crtc->layer_nr,
> num_planes),
> - mtk_ddp_comp_supported_rotations(comp));
> + mtk_ddp_comp_supported_rotations(comp),
> + supports_10bit);
> if (ret)
> return ret;
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_plane.c b/drivers/gpu/drm/mediatek/mtk_drm_plane.c
> index d54fbf34b000..7fe5c47b4d50 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_plane.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_plane.c
> @@ -12,6 +12,8 @@
> #include <drm/drm_framebuffer.h>
> #include <drm/drm_gem_atomic_helper.h>
> #include <linux/align.h>
> +#include <drm/drm_plane_helper.h>
> +#include <linux/of.h>
>
> #include "mtk_drm_crtc.h"
> #include "mtk_drm_ddp_comp.h"
> @@ -19,7 +21,7 @@
> #include "mtk_drm_gem.h"
> #include "mtk_drm_plane.h"
>
> -static const u32 formats[] = {
> +static const u32 default_formats[] = {
> DRM_FORMAT_XRGB8888,
> DRM_FORMAT_ARGB8888,
> DRM_FORMAT_BGRX8888,
> @@ -41,6 +43,22 @@ static const u64 modifiers[] = {
> DRM_FORMAT_MOD_INVALID,
> };
>
> +static const u32 formats_with_10bit_cap[] = {
> + DRM_FORMAT_XRGB8888,
> + DRM_FORMAT_ARGB8888,
> + DRM_FORMAT_ARGB2101010,
> + DRM_FORMAT_BGRX8888,
> + DRM_FORMAT_BGRA8888,
> + DRM_FORMAT_BGRA1010102,
> + DRM_FORMAT_ABGR8888,
> + DRM_FORMAT_XBGR8888,
> + DRM_FORMAT_RGB888,
> + DRM_FORMAT_BGR888,
> + DRM_FORMAT_RGB565,
> + DRM_FORMAT_UYVY,
> + DRM_FORMAT_YUYV,
> +};
I would like to move these array to ovl/rdma driver and query these
array with ovl/rdma driver (struct mtk_ddp_comp *comp in
mtk_drm_crtc_init_comp_planes()).
Regards,
Chun-Kuang.
> +
> static void mtk_plane_reset(struct drm_plane *plane)
> {
> struct mtk_plane_state *state;
> @@ -315,13 +333,24 @@ static const struct drm_plane_helper_funcs mtk_plane_helper_funcs = {
>
> int mtk_plane_init(struct drm_device *dev, struct drm_plane *plane,
> unsigned long possible_crtcs, enum drm_plane_type type,
> - unsigned int supported_rotations)
> + unsigned int supported_rotations, bool supports_10bit)
> {
> int err;
>
> - err = drm_universal_plane_init(dev, plane, possible_crtcs,
> - &mtk_plane_funcs, formats,
> - ARRAY_SIZE(formats), modifiers, type, NULL);
> + if (supports_10bit) {
> + err = drm_universal_plane_init(dev, plane, possible_crtcs,
> + &mtk_plane_funcs,
> + formats_with_10bit_cap,
> + ARRAY_SIZE(formats_with_10bit_cap),
> + modifiers, type, NULL);
> + } else {
> + err = drm_universal_plane_init(dev, plane, possible_crtcs,
> + &mtk_plane_funcs,
> + default_formats,
> + ARRAY_SIZE(default_formats),
> + modifiers, type, NULL);
> + }
> +
> if (err) {
> DRM_ERROR("failed to initialize plane\n");
> return err;
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_plane.h b/drivers/gpu/drm/mediatek/mtk_drm_plane.h
> index 8f39011cdbfc..d3e6f29a1e25 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_plane.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_plane.h
> @@ -48,6 +48,6 @@ to_mtk_plane_state(struct drm_plane_state *state)
>
> int mtk_plane_init(struct drm_device *dev, struct drm_plane *plane,
> unsigned long possible_crtcs, enum drm_plane_type type,
> - unsigned int supported_rotations);
> + unsigned int supported_rotations, bool supports_10bit);
>
> #endif
> --
> 2.39.0.314.g84b9a713c41-goog
>
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