[RFC 1/8] drm/i915: Skip clflush after GPU writes on Meteorlake

Matt Roper matthew.d.roper at intel.com
Thu Jul 27 22:19:16 UTC 2023


On Thu, Jul 27, 2023 at 03:54:57PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
> 
> On Meteorlake CPU cache will not contain stale data after GPU access since
> write-invalidate protocol is used, which means there is no need to flush
> before potentially transitioning the buffer to a non-coherent domain.
> 
> Use the opportunity to documet the situation on discrete too.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
> Cc: Matt Roper <matthew.d.roper at intel.com>
> Cc: Fei Yang <fei.yang at intel.com>
> Cc: Matthew Auld <matthew.auld at intel.com>
> Cc: Thomas Hellström <thomas.hellstrom at linux.intel.com>

Reviewed-by: Matt Roper <matthew.d.roper at intel.com>

> ---
>  drivers/gpu/drm/i915/gem/i915_gem_domain.c | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
> index ffddec1d2a76..57db9c581bf6 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
> @@ -24,9 +24,22 @@ static bool gpu_write_needs_clflush(struct drm_i915_gem_object *obj)
>  {
>  	struct drm_i915_private *i915 = to_i915(obj->base.dev);
>  
> +	/*
> +	 * Discrete GPUs never dirty the CPU cache.
> +	 */
>  	if (IS_DGFX(i915))
>  		return false;
>  
> +	/*
> +	 * Cache snooping on Meteorlake is using write-invalidate so GPU writes
> +	 * never end up in the CPU cache.
> +	 *
> +	 * QQQ: Do other snooping platforms behave identicaly and could we
> +	 *      therefore write this as "if !HAS_LLC(i915) && HAS_SNOOP(i915)"?
> +	 */
> +	if (IS_METEORLAKE(i915))
> +		return false;
> +
>  	/*
>  	 * For objects created by userspace through GEM_CREATE with pat_index
>  	 * set by set_pat extension, i915_gem_object_has_cache_level() will
> -- 
> 2.39.2
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation


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