[PATCH v2 5/7] drm/msm/dpu: use MDSS data for programming SSPP
Abhinav Kumar
quic_abhinavk at quicinc.com
Fri Jul 28 22:03:24 UTC 2023
On 7/28/2023 2:39 PM, Dmitry Baryshkov wrote:
> On 29/07/2023 00:36, Abhinav Kumar wrote:
>>
>>
>> On 7/28/2023 2:33 PM, Dmitry Baryshkov wrote:
>>> Switch to using data from MDSS driver to program the SSPP fetch and UBWC
>>> configuration. As a side-effect, this also swithes the DPU driver from
>>> DPU_HW_UBWC_VER_xx values to the UBWC_x_y enum, which reflects
>>> the hardware register values.
>>>
>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov at linaro.org>
>>> ---
>>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 18 ++++++++++--------
>>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 6 +++---
>>> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 16 +++++++++++++++-
>>> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 1 +
>>> drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 3 ++-
>>> drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 2 ++
>>> 6 files changed, 33 insertions(+), 13 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
>>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
>>> index b364cf75bb3f..f2192de93713 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
>>> @@ -8,6 +8,8 @@
>>> #include "dpu_hw_sspp.h"
>>> #include "dpu_kms.h"
>>> +#include "msm_mdss.h"
>>> +
>>> #include <drm/drm_file.h>
>>> #define DPU_FETCH_CONFIG_RESET_VALUE 0x00000087
>>> @@ -270,26 +272,26 @@ static void dpu_hw_sspp_setup_format(struct
>>> dpu_sw_pipe *pipe,
>>> DPU_REG_WRITE(c, SSPP_FETCH_CONFIG,
>>> DPU_FETCH_CONFIG_RESET_VALUE |
>>> ctx->ubwc->highest_bank_bit << 18);
>>> - switch (ctx->ubwc->ubwc_version) {
>>> - case DPU_HW_UBWC_VER_10:
>>> + switch (ctx->ubwc->ubwc_enc_version) {
>>
>> Didnt we agree to protect this with if (ctx->ubwc) ?
>
> Yes. However ctx->ubwc is set to mdss_data and in dpu_kms_hw_init() we
> ensure that mdss_data is not NULL, so this check is not necessary.
>
Ack
Reviewed-by: Abhinav Kumar <quic_abhinavk at quicinc.com>
>>
>>> + case UBWC_1_0:
>>> fast_clear = fmt->alpha_enable ? BIT(31) : 0;
>>> DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
>>> fast_clear | (ctx->ubwc->ubwc_swizzle & 0x1) |
>>> BIT(8) |
>>> (ctx->ubwc->highest_bank_bit << 4));
>>> break;
>>> - case DPU_HW_UBWC_VER_20:
>>> + case UBWC_2_0:
>>> fast_clear = fmt->alpha_enable ? BIT(31) : 0;
>>> DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
>>> fast_clear | (ctx->ubwc->ubwc_swizzle) |
>>> (ctx->ubwc->highest_bank_bit << 4));
>>> break;
>>> - case DPU_HW_UBWC_VER_30:
>>> + case UBWC_3_0:
>>> DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
>>> BIT(30) | (ctx->ubwc->ubwc_swizzle) |
>>> (ctx->ubwc->highest_bank_bit << 4));
>>> break;
>>> - case DPU_HW_UBWC_VER_40:
>>> + case UBWC_4_0:
>>> DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
>>> DPU_FORMAT_IS_YUV(fmt) ? 0 : BIT(30));
>>> break;
>>> @@ -670,11 +672,11 @@ int _dpu_hw_sspp_init_debugfs(struct
>>> dpu_hw_sspp *hw_pipe, struct dpu_kms *kms,
>>> #endif
>>> struct dpu_hw_sspp *dpu_hw_sspp_init(const struct dpu_sspp_cfg *cfg,
>>> - void __iomem *addr, const struct dpu_ubwc_cfg *ubwc)
>>> + void __iomem *addr, const struct msm_mdss_data *mdss_data)
>>> {
>>> struct dpu_hw_sspp *hw_pipe;
>>> - if (!addr || !ubwc)
>>> + if (!addr)
>>> return ERR_PTR(-EINVAL);
>>> hw_pipe = kzalloc(sizeof(*hw_pipe), GFP_KERNEL);
>>> @@ -685,7 +687,7 @@ struct dpu_hw_sspp *dpu_hw_sspp_init(const struct
>>> dpu_sspp_cfg *cfg,
>>> hw_pipe->hw.log_mask = DPU_DBG_MASK_SSPP;
>>> /* Assign ops */
>>> - hw_pipe->ubwc = ubwc;
>>> + hw_pipe->ubwc = mdss_data;
>>> hw_pipe->idx = cfg->id;
>>> hw_pipe->cap = cfg;
>>> _setup_layer_ops(hw_pipe, hw_pipe->cap->features);
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
>>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
>>> index 085f34bc6b88..cbf4f95ff0fd 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
>>> @@ -317,7 +317,7 @@ struct dpu_hw_sspp_ops {
>>> struct dpu_hw_sspp {
>>> struct dpu_hw_blk base;
>>> struct dpu_hw_blk_reg_map hw;
>>> - const struct dpu_ubwc_cfg *ubwc;
>>> + const struct msm_mdss_data *ubwc;
>>> /* Pipe */
>>> enum dpu_sspp idx;
>>> @@ -333,10 +333,10 @@ struct dpu_kms;
>>> * Should be called once before accessing every pipe.
>>> * @cfg: Pipe catalog entry for which driver object is required
>>> * @addr: Mapped register io address of MDP
>>> - * @ubwc: UBWC configuration data
>>> + * @mdss_data: UBWC / MDSS configuration data
>>> */
>>> struct dpu_hw_sspp *dpu_hw_sspp_init(const struct dpu_sspp_cfg *cfg,
>>> - void __iomem *addr, const struct dpu_ubwc_cfg *ubwc);
>>> + void __iomem *addr, const struct msm_mdss_data *mdss_data);
>>> /**
>>> * dpu_hw_sspp_destroy(): Destroys SSPP driver context
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>>> index c1d06e19b237..2da9eef687af 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>>> @@ -22,6 +22,7 @@
>>> #include "msm_drv.h"
>>> #include "msm_mmu.h"
>>> +#include "msm_mdss.h"
>>> #include "msm_gem.h"
>>> #include "disp/msm_disp_snapshot.h"
>>> @@ -1124,7 +1125,20 @@ static int dpu_kms_hw_init(struct msm_kms *kms)
>>> goto power_error;
>>> }
>>> - rc = dpu_rm_init(&dpu_kms->rm, dpu_kms->catalog, dpu_kms->mmio);
>>> + dpu_kms->mdss = msm_mdss_get_mdss_data(dpu_kms->pdev->dev.parent);
>>> + if (IS_ERR(dpu_kms->mdss)) {
>>> + rc = PTR_ERR(dpu_kms->mdss);
>>> + DPU_ERROR("failed to get MDSS data: %d\n", rc);
>>> + goto power_error;
>>> + }
>>> +
>>> + if (!dpu_kms->mdss) {
>>> + rc = -EINVAL;
>>> + DPU_ERROR("NULL MDSS data\n");
>>> + goto power_error;
>>> + }
>>> +
>>> + rc = dpu_rm_init(&dpu_kms->rm, dpu_kms->catalog, dpu_kms->mdss,
>>> dpu_kms->mmio);
>>> if (rc) {
>>> DPU_ERROR("rm init failed: %d\n", rc);
>>> goto power_error;
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
>>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
>>> index f3bdd4f11108..b6f53ca6e962 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
>>> @@ -67,6 +67,7 @@ struct dpu_kms {
>>> struct msm_kms base;
>>> struct drm_device *dev;
>>> const struct dpu_mdss_cfg *catalog;
>>> + const struct msm_mdss_data *mdss;
>>> /* io/register spaces: */
>>> void __iomem *mmio, *vbif[VBIF_MAX];
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
>>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
>>> index 4a53e2c931d6..f9215643c71a 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
>>> @@ -101,6 +101,7 @@ int dpu_rm_destroy(struct dpu_rm *rm)
>>> int dpu_rm_init(struct dpu_rm *rm,
>>> const struct dpu_mdss_cfg *cat,
>>> + const struct msm_mdss_data *mdss_data,
>>> void __iomem *mmio)
>>> {
>>> int rc, i;
>>> @@ -230,7 +231,7 @@ int dpu_rm_init(struct dpu_rm *rm,
>>> struct dpu_hw_sspp *hw;
>>> const struct dpu_sspp_cfg *sspp = &cat->sspp[i];
>>> - hw = dpu_hw_sspp_init(sspp, mmio, cat->ubwc);
>>> + hw = dpu_hw_sspp_init(sspp, mmio, mdss_data);
>>> if (IS_ERR(hw)) {
>>> rc = PTR_ERR(hw);
>>> DPU_ERROR("failed sspp object creation: err %d\n", rc);
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
>>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
>>> index d62c2edb2460..2b551566cbf4 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
>>> @@ -40,11 +40,13 @@ struct dpu_rm {
>>> * for all HW blocks.
>>> * @rm: DPU Resource Manager handle
>>> * @cat: Pointer to hardware catalog
>>> + * @mdss_data: Pointer to MDSS / UBWC configuration
>>> * @mmio: mapped register io address of MDP
>>> * @Return: 0 on Success otherwise -ERROR
>>> */
>>> int dpu_rm_init(struct dpu_rm *rm,
>>> const struct dpu_mdss_cfg *cat,
>>> + const struct msm_mdss_data *mdss_data,
>>> void __iomem *mmio);
>>> /**
>
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