[PATCH 4/7] drm/msm/dpu: enable INTF TE operations only when supported by HW

[Dmitry Baryshkov]

On 27/07/2023 23:12, Marijn Suijten wrote:
> On 2023-07-27 19:21:01, Dmitry Baryshkov wrote:
>> The DPU_INTF_TE bit is set for all INTF blocks on DPU >= 5.0, however
>> only INTF_1 and INTF_2 actually support tearing control. Rather than
>> trying to fix the DPU_INTF_TE, check for the presense of the
> 
> I would more exactly expand "fix" to "Rather than specifying that
> feature bit on DSI INTF_1 and INTF_2 exclusively..."
> 
>> corresponding interrupt line.
> 
> ... which the catalog will only provide on DPU >= 5.0.

I'm going to rephrase this in a slightly different way to follow the irq 
presence -> major & type change.

> 
>>
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov at linaro.org>
> 
> Reviewed-by: Marijn Suijten <marijn.suijten at somainline.org>
> 
>> ---
>>   drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
>> index 7ca772791a73..8abdf9553f3b 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
>> @@ -557,7 +557,7 @@ struct dpu_hw_intf *dpu_hw_intf_init(const struct dpu_intf_cfg *cfg,
>>   	c->ops.setup_misr = dpu_hw_intf_setup_misr;
>>   	c->ops.collect_misr = dpu_hw_intf_collect_misr;
>>   
>> -	if (cfg->features & BIT(DPU_INTF_TE)) {
>> +	if (cfg->intr_tear_rd_ptr) {
>>   		c->ops.enable_tearcheck = dpu_hw_intf_enable_te;
>>   		c->ops.disable_tearcheck = dpu_hw_intf_disable_te;
>>   		c->ops.connect_external_te = dpu_hw_intf_connect_external_te;
>> -- 
>> 2.39.2
>>

-- 
With best wishes
Dmitry