[PATCH v4 2/4] drm/msm/dpu: add DSPPs into reservation upon a CTM request
Yongqin Liu
yongqin.liu at linaro.org
Sat Jun 10 10:26:58 UTC 2023
Hi, Kalyan Thota
It seems this change caused some drm problems with the Android build.
I tested with one Android build that based on the ACK android-mainline
kernel[1], and there are the message printed like
01-01 06:51:50.541 504 504 E :
[drm:_dpu_rm_check_lm_and_get_connected_blks] [dpu error]failed to get
dspp on lm 0
01-01 06:51:50.551 504 504 E :
[drm:_dpu_rm_check_lm_and_get_connected_blks] [dpu error]failed to get
dspp on lm 0
01-01 06:51:50.560 504 504 E :
[drm:_dpu_rm_check_lm_and_get_connected_blks] [dpu error]failed to get
dspp on lm 0
01-01 06:51:50.570 504 504 E :
[drm:_dpu_rm_check_lm_and_get_connected_blks] [dpu error]failed to get
dspp on lm 0
01-01 06:51:50.579 504 504 E :
[drm:_dpu_rm_make_reservation] [dpu error]unable to find appropriate
mixers
01-01 06:51:50.588 504 504 E : [drm:dpu_rm_reserve]
[dpu error]failed to reserve hw resources: -119
For details, please check the link here: https://termbin.com/31lc
If I revert this commit, then the problem will be gone.
Could you please help check if there is any problem with this commit?
[1]: https://android.googlesource.com/kernel/common/+/refs/heads/android-mainline
Thanks,
Yongqin Liu
On Wed, 1 Mar 2023 at 16:24, Marijn Suijten
<marijn.suijten at somainline.org> wrote:
>
> On 2023-02-13 03:11:42, Kalyan Thota wrote:
> > Add DSPP blocks into the topology for reservation, if there
> > is a CTM request for that composition.
> >
> > Signed-off-by: Kalyan Thota <quic_kalyant at quicinc.com>
> > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov at linaro.org>
>
> Reviewed-by: Marijn Suijten <marijn.suijten at somainline.org>
>
> > ---
> > Changes in v1:
> > - Minor nits (Dmitry)
> >
> > Changes in v2:
> > - Populate DSPPs into the reservation only if CTM is requested (Dmitry)
> > ---
> > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 15 ++++++---------
> > 1 file changed, 6 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > index 9c6817b..46d2a5c 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > @@ -545,7 +545,8 @@ bool dpu_encoder_use_dsc_merge(struct drm_encoder *drm_enc)
> > static struct msm_display_topology dpu_encoder_get_topology(
> > struct dpu_encoder_virt *dpu_enc,
> > struct dpu_kms *dpu_kms,
> > - struct drm_display_mode *mode)
> > + struct drm_display_mode *mode,
> > + struct drm_crtc_state *crtc_state)
> > {
> > struct msm_display_topology topology = {0};
> > int i, intf_count = 0;
> > @@ -563,8 +564,7 @@ static struct msm_display_topology dpu_encoder_get_topology(
> > * 1 LM, 1 INTF
> > * 2 LM, 1 INTF (stream merge to support high resolution interfaces)
> > *
> > - * Adding color blocks only to primary interface if available in
> > - * sufficient number
> > + * Add dspps to the reservation requirements if ctm is requested
> > */
> > if (intf_count == 2)
> > topology.num_lm = 2;
> > @@ -573,11 +573,8 @@ static struct msm_display_topology dpu_encoder_get_topology(
> > else
> > topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1;
> >
> > - if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI) {
> > - if (dpu_kms->catalog->dspp &&
> > - (dpu_kms->catalog->dspp_count >= topology.num_lm))
> > - topology.num_dspp = topology.num_lm;
> > - }
> > + if (crtc_state->ctm)
> > + topology.num_dspp = topology.num_lm;
> >
> > topology.num_enc = 0;
> > topology.num_intf = intf_count;
> > @@ -643,7 +640,7 @@ static int dpu_encoder_virt_atomic_check(
> > }
> > }
> >
> > - topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode);
> > + topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode, crtc_state);
> >
> > /* Reserve dynamic resources now. */
> > if (!ret) {
> > --
> > 2.7.4
> >
--
Best Regards,
Yongqin Liu
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