[Freedreno] [PATCH 3/3] drm/msm/dsi: Enable DATABUS_WIDEN for DSI command mode

[Marijn Suijten]

On 2023-06-23 13:34:06, Abhinav Kumar wrote:
> 
> 
> On 6/23/2023 1:14 PM, Marijn Suijten wrote:
> > On 2023-06-23 10:29:51, Abhinav Kumar wrote:
> > <snip>
> >> The concept is quite simple
> >>
> >> one pixel per clock for uncompresssed without widebubus
> >>
> >> 2 pixels per clock for uncompressed with widebus (only enabled for DP
> >> not DSI)
> >>
> >> 3 bytes worth of data for compressed without widebus
> >>
> >> 6 bytes worth of data for compressed with widebus
> >>
> >> When compression happens, we cannot quantify with pixels as the boundary
> >> is not defined with respect to bytes.
> >>
> >> You brought up uncompressed in your below comment so I assumed your
> >> question of /2 was about uncompressed too.
> > 
> > No clue where things are going wrong, but you either avoid or
> > misunderstand the question.
> > 
> > (Talking exclusively about compressed data here!)
> > 
> > pclk is determined based on the number of bytes.
> > 
> > When widebus is enabled, we transfer twice as many bytes per pclk cycle.
> > 
> > Can pclk be reduced by a factor two, as that should still be enough to
> > transfer the same amount of bytes when widebus is enabled?
> > 
> 
> I dont know where the misunderstanding is too.
> 
> I already did answer that pclk can be /2 for uncompressed.

Except that my question is about compressed.

> But for compressed it will be divided by the compression ration.

The question here is "why exactly"?  I am looking for the argument that
justifies pclk being twice as high for the number of bytes we need to
send.

Is that answer: pclk is not only used for the bus between DPU and DSI?

If the answer to that question is yes, then I'd ask what the advantage
is of widebus.

<snip>

Let's leave the rest for what it is.

- Marijn