[PATCH 4/7] drm/i915: Enable YCbCr420 for VDSC
Shankar, Uma
uma.shankar at intel.com
Wed Mar 8 10:59:47 UTC 2023
> -----Original Message-----
> From: Kandpal, Suraj <suraj.kandpal at intel.com>
> Sent: Wednesday, February 22, 2023 11:02 AM
> To: dri-devel at lists.freedesktop.org; intel-gfx at lists.freedesktop.org
> Cc: Shankar, Uma <uma.shankar at intel.com>; Nautiyal, Ankit K
> <ankit.k.nautiyal at intel.com>; Kandpal, Suraj <suraj.kandpal at intel.com>; Kulkarni,
> Vandita <vandita.kulkarni at intel.com>
> Subject: [PATCH 4/7] drm/i915: Enable YCbCr420 for VDSC
drm/i915/dsc is better
Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar at intel.com>
> Implementation of VDSC for YCbCr420.
> Add QP tables for 8,10,12 BPC from rc_tables.h in intel_qp_tables.c (Derived from C-
> Model, which is given along with DSC1.2a Spec from Vesa)
> intel_lookup_range_min/max_qp functons need to take into account the output
> format. Based on that appropriate qp table need to be chosen.
> Other rc_parameters need to be set where currently values for 444 format is
> hardcoded in calculate_rc_parameters( ).
> vdsc_cfg struct needs to be filled with output format information, where these are
> hardcoded for 444 format.
> Bspec: 49259
> Signed-off-by: Suraj Kandpal <suraj.kandpal at intel.com>
> Reviewed-by: Vandita Kulkarni <Vandita.kulkarni at intel.com>
> ---
> .../gpu/drm/i915/display/intel_qp_tables.c | 187 ++++++++++++++++--
> .../gpu/drm/i915/display/intel_qp_tables.h | 4 +-
> drivers/gpu/drm/i915/display/intel_vdsc.c | 4 +-
> 3 files changed, 180 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_qp_tables.c
> b/drivers/gpu/drm/i915/display/intel_qp_tables.c
> index 6f8e4ec5c0fb..6e86c0971d24 100644
> --- a/drivers/gpu/drm/i915/display/intel_qp_tables.c
> +++ b/drivers/gpu/drm/i915/display/intel_qp_tables.c
> @@ -17,6 +17,15 @@
> /* from BPP 6 to 36 in steps of 0.5 */
> #define RC_RANGE_QP444_12BPC_MAX_NUM_BPP 61
>
> +/* from BPP 6 to 24 in steps of 0.5 */
> +#define RC_RANGE_QP420_8BPC_MAX_NUM_BPP 17
> +
> +/* from BPP 6 to 30 in steps of 0.5 */
> +#define RC_RANGE_QP420_10BPC_MAX_NUM_BPP 23
> +
> +/* from BPP 6 to 36 in steps of 0.5 */
> +#define RC_RANGE_QP420_12BPC_MAX_NUM_BPP 29
> +
> /*
> * These qp tables are as per the C model
> * and it has the rows pointing to bpps which increment @@ -283,26 +292,182 @@
> static const u8
> rc_range_maxqp444_12bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP444_12BPC
> 11, 11, 10, 10, 10, 10, 10, 9, 9, 8, 8, 8, 8, 8, 7, 7, 6, 6, 6, 6, 5, 5, 4 } };
>
> -#define PARAM_TABLE(_minmax, _bpc, _row, _col) do { \
> - if (bpc == (_bpc)) \
> - return rc_range_##_minmax##qp444_##_bpc##bpc[_row][_col]; \
> +static const u8
> rc_range_minqp420_8bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP420_8BPC_MA
> X_NUM_BPP] = {
> + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
> + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
> + { 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
> + { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
> + { 3, 3, 3, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0 },
> + { 3, 3, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0 },
> + { 3, 3, 3, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 0, 0 },
> + { 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 0 },
> + { 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 0 },
> + { 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 1, 1 },
> + { 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 3, 3, 3, 3, 2, 1, 1 },
> + { 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 3, 2, 2, 1 },
> + { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 3, 3, 2, 1 },
> + { 9, 8, 8, 7, 7, 7, 7, 7, 7, 6, 5, 5, 4, 3, 3, 3, 2 },
> + { 13, 12, 12, 11, 10, 10, 9, 8, 8, 7, 6, 6, 5, 5, 4, 4, 3 } };
> +
> +static const u8
> rc_range_maxqp420_8bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP420_8BPC_MA
> X_NUM_BPP] = {
> + { 4, 4, 3, 3, 2, 2, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
> + { 4, 4, 4, 4, 4, 3, 2, 2, 1, 1, 1, 1, 0, 0, 0, 0, 0 },
> + { 5, 5, 5, 5, 5, 4, 3, 2, 1, 1, 1, 1, 1, 1, 0, 0, 0 },
> + { 6, 6, 6, 6, 6, 5, 4, 3, 2, 2, 2, 1, 1, 1, 1, 0, 0 },
> + { 7, 7, 7, 7, 7, 5, 4, 3, 2, 2, 2, 2, 2, 1, 1, 1, 0 },
> + { 7, 7, 7, 7, 7, 6, 5, 4, 3, 3, 3, 2, 2, 2, 1, 1, 0 },
> + { 7, 7, 7, 7, 7, 6, 5, 4, 3, 3, 3, 3, 2, 2, 2, 1, 1 },
> + { 8, 8, 8, 8, 8, 7, 6, 5, 4, 4, 4, 3, 3, 2, 2, 2, 1 },
> + { 9, 9, 9, 8, 8, 7, 6, 6, 5, 5, 4, 4, 3, 3, 2, 2, 1 },
> + { 10, 10, 9, 9, 9, 8, 7, 6, 5, 5, 5, 4, 4, 3, 3, 2, 2 },
> + { 10, 10, 10, 9, 9, 8, 8, 7, 6, 6, 5, 5, 4, 4, 3, 2, 2 },
> + { 11, 11, 10, 10, 9, 9, 8, 7, 7, 6, 6, 5, 5, 4, 3, 3, 2 },
> + { 11, 11, 11, 10, 9, 9, 9, 8, 7, 7, 6, 5, 5, 4, 4, 3, 2 },
> + { 13, 12, 12, 11, 10, 10, 9, 8, 8, 7, 6, 6, 5, 4, 4, 4, 3 },
> + { 14, 13, 13, 12, 11, 11, 10, 9, 9, 8, 7, 7, 6, 6, 5, 5, 4 } };
> +
> +static const u8
> rc_range_minqp420_10bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP420_10BPC_
> MAX_NUM_BPP] = {
> + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
> + { 4, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
> + { 4, 4, 4, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
> + { 5, 5, 5, 4, 4, 4, 4, 4, 4, 3, 3, 2, 2, 2, 2, 1, 0, 0, 0, 0, 0, 0, 0 },
> + { 7, 7, 7, 6, 6, 5, 5, 4, 4, 3, 3, 3, 3, 2, 2, 2, 1, 1, 1, 0, 0, 0, 0 },
> + { 7, 7, 7, 7, 7, 6, 5, 5, 5, 5, 5, 4, 3, 3, 2, 2, 1, 1, 1, 1, 1, 0, 0 },
> + { 7, 7, 7, 7, 7, 6, 6, 5, 5, 5, 5, 4, 4, 4, 3, 2, 2, 2, 2, 1, 1, 1, 0 },
> + { 7, 7, 7, 7, 7, 7, 6, 6, 6, 6, 6, 5, 4, 4, 4, 3, 2, 2, 2, 1, 1, 1, 0 },
> + { 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 6, 6, 5, 5, 4, 4, 3, 3, 2, 2, 2, 1, 1 },
> + { 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 5, 5, 4, 4, 3, 3, 2, 2, 1, 1 },
> + { 9, 9, 9, 9, 9, 8, 8, 8, 8, 8, 7, 7, 6, 6, 5, 5, 4, 4, 3, 3, 2, 2, 1 },
> + { 9, 9, 9, 9, 9, 9, 8, 8, 8, 8, 8, 8, 8, 7, 6, 6, 5, 4, 4, 3, 3, 2, 1 },
> + { 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 8, 8, 7, 7, 6, 5, 4, 4, 3, 3, 2, 1 },
> + { 13, 12, 12, 11, 11, 11, 11, 11, 11, 10, 9, 9, 8, 7, 7, 6, 5, 5, 4, 3, 3,
> + 2, 2 },
> + { 17, 16, 16, 15, 14, 14, 13, 12, 12, 11, 10, 10, 10, 9, 8, 8, 7, 6, 6, 5,
> + 5, 4, 4 }
> +};
> +
> +static const u8
> rc_range_maxqp420_10bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP420_10BPC_
> MAX_NUM_BPP] = {
> + { 8, 8, 7, 6, 4, 4, 3, 3, 2, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
> + { 8, 8, 8, 7, 6, 5, 4, 4, 3, 3, 3, 3, 2, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 },
> + { 9, 9, 9, 8, 8, 7, 6, 5, 4, 3, 3, 3, 3, 3, 2, 1, 1, 1, 0, 0, 0, 0, 0 },
> + { 10, 10, 10, 9, 9, 8, 7, 6, 5, 4, 4, 3, 3, 3, 3, 2, 1, 1, 1, 1, 1, 0,
> + 0 },
> + { 11, 11, 11, 10, 10, 8, 7, 6, 5, 4, 4, 4, 4, 3, 3, 3, 2, 2, 2, 1, 1, 1,
> + 0 },
> + { 11, 11, 11, 10, 10, 9, 8, 7, 6, 6, 6, 5, 4, 4, 3, 3, 2, 2, 2, 2, 2, 1,
> + 1 },
> + { 11, 11, 11, 11, 11, 10, 9, 8, 7, 7, 7, 6, 5, 5, 4, 3, 3, 3, 3, 2, 2, 2,
> + 1 },
> + { 12, 12, 12, 12, 12, 11, 10, 9, 8, 8, 8, 7, 6, 5, 5, 4, 3, 3, 3, 2, 2,
> + 2, 1 },
> + { 13, 13, 13, 12, 12, 11, 10, 10, 9, 9, 8, 8, 7, 7, 6, 5, 4, 4, 3, 3, 3,
> + 2, 2 },
> + { 14, 14, 13, 13, 13, 12, 11, 10, 9, 9, 9, 8, 8, 7, 7, 6, 5, 4, 4, 3, 3,
> + 2, 2 },
> + { 14, 14, 14, 13, 13, 12, 12, 11, 10, 10, 9, 9, 8, 8, 7, 6, 5, 5, 4, 4,
> + 3, 3, 2 },
> + { 15, 15, 14, 14, 13, 13, 12, 11, 11, 10, 10, 9, 9, 8, 7, 7, 6, 5, 5, 4,
> + 4, 3, 2 },
> + { 15, 15, 15, 14, 13, 13, 13, 12, 11, 11, 10, 9, 9, 8, 8, 7, 6, 5, 5, 4,
> + 4, 3, 2 },
> + { 17, 16, 16, 15, 14, 14, 13, 12, 12, 11, 10, 10, 9, 8, 8, 7, 6, 6, 5, 4,
> + 4, 3, 3 },
> + { 18, 17, 17, 16, 15, 15, 14, 13, 13, 12, 11, 11, 11, 10, 9, 9, 8, 7, 7,
> + 6, 6, 5, 5 }
> +};
> +
> +static const u8
> rc_range_minqp420_12bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP420_12BPC_
> MAX_NUM_BPP] = {
> + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
> + 0, 0, 0, 0, 0 },
> + { 4, 4, 4, 4, 4, 4, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0,
> + 0, 0, 0, 0, 0 },
> + { 9, 8, 8, 7, 7, 6, 5, 5, 4, 4, 4, 4, 3, 3, 3, 2, 2, 1, 0, 0, 0, 0, 0, 0,
> + 0, 0, 0, 0, 0 },
> + { 10, 9, 9, 8, 8, 8, 7, 7, 6, 6, 6, 5, 5, 4, 4, 3, 2, 2, 1, 1, 1, 0, 0, 0,
> + 0, 0, 0, 0, 0 },
> + { 11, 10, 10, 10, 10, 9, 9, 8, 7, 6, 6, 6, 6, 5, 5, 4, 3, 3, 3, 2, 2, 1,
> + 0, 0, 0, 0, 0, 0, 0 },
> + { 11, 11, 11, 11, 11, 10, 10, 9, 9, 9, 9, 8, 7, 6, 5, 5, 4, 4, 3, 3, 3, 2,
> + 1, 1, 0, 0, 0, 0, 0 },
> + { 11, 11, 11, 11, 11, 11, 10, 10, 9, 9, 9, 8, 8, 7, 6, 5, 5, 5, 5, 4, 3, 3,
> + 2, 1, 1, 1, 1, 1, 0 },
> + { 11, 11, 11, 11, 11, 11, 11, 10, 10, 10, 10, 9, 8, 8, 8, 7, 6, 6, 5, 4, 4,
> + 3, 2, 2, 1, 1, 1, 1, 1 },
> + { 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 10, 10, 9, 9, 8, 8, 7, 7, 6, 5,
> + 5, 4, 4, 2, 2, 1, 1, 1, 1 },
> + { 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 10, 10, 9, 9, 8, 8, 7, 7, 6,
> + 5, 4, 4, 3, 2, 2, 1, 1, 1 },
> + { 13, 13, 13, 13, 13, 13, 13, 12, 12, 12, 11, 11, 10, 10, 9, 9, 8, 8, 7, 7,
> + 6, 5, 4, 3, 3, 2, 2, 1, 1 },
> + { 13, 13, 13, 13, 13, 13, 13, 13, 13, 12, 12, 12, 12, 11, 10, 10, 9, 8, 8,
> + 7, 7, 6, 5, 4, 3, 3, 2, 2, 1 },
> + { 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 12, 12, 11, 11, 10, 9, 8, 8,
> + 7, 7, 6, 5, 4, 4, 3, 2, 2, 1 },
> + { 15, 15, 15, 15, 15, 15, 15, 15, 15, 14, 13, 13, 12, 11, 11, 10, 9, 9, 8,
> + 8, 7, 6, 6, 5, 4, 4, 3, 3, 2 },
> + { 21, 20, 20, 19, 18, 18, 17, 16, 16, 15, 14, 14, 14, 13, 12, 12, 11, 10,
> + 10, 10, 9, 8, 8, 7, 6, 6, 5, 5, 4 }
> +};
> +
> +static const u8
> rc_range_maxqp420_12bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP420_12BPC_
> MAX_NUM_BPP] = {
> + { 11, 10, 9, 8, 6, 6, 5, 5, 4, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 0, 0,
> + 0, 0, 0, 0, 0, 0 },
> + { 12, 11, 11, 10, 9, 8, 7, 7, 6, 6, 5, 5, 4, 3, 3, 2, 1, 1, 1, 1, 1, 1,
> + 1, 0, 0, 0, 0, 0, 0 },
> + { 13, 12, 12, 11, 11, 10, 9, 8, 7, 6, 6, 6, 5, 5, 4, 3, 3, 2, 1, 1, 1, 1,
> + 1, 0, 0, 0, 0, 0, 0 },
> + { 14, 13, 13, 12, 12, 11, 10, 9, 8, 7, 7, 6, 6, 5, 5, 4, 3, 3, 2, 2, 2, 1,
> + 1, 1, 0, 0, 0, 0, 0 },
> + { 15, 14, 14, 13, 13, 11, 10, 9, 8, 7, 7, 7, 7, 6, 6, 5, 4, 4, 4, 3, 3, 2,
> + 1, 1, 1, 0, 0, 0, 0 },
> + { 15, 15, 15, 14, 14, 13, 12, 11, 10, 10, 10, 9, 8, 7, 6, 6, 5, 5, 4, 4,
> + 4, 3, 2, 2, 1, 1, 0, 0, 0 },
> + { 15, 15, 15, 15, 15, 14, 13, 12, 11, 11, 11, 10, 9, 8, 7, 6, 6, 6, 6, 5,
> + 4, 4, 3, 2, 2, 2, 1, 1, 0 },
> + { 16, 16, 16, 16, 16, 15, 14, 13, 12, 12, 12, 11, 10, 9, 9, 8, 7, 7, 6, 5,
> + 5, 4, 3, 3, 2, 2, 2, 1, 1 },
> + { 17, 17, 17, 16, 16, 15, 14, 14, 13, 13, 12, 12, 11, 11, 10, 9, 8, 8, 7,
> + 6, 6, 5, 5, 3, 3, 2, 2, 1, 1 },
> + { 18, 18, 17, 17, 17, 16, 15, 14, 13, 13, 13, 12, 12, 11, 11, 10, 9, 8, 8,
> + 7, 6, 5, 5, 4, 3, 3, 2, 2, 1 },
> + { 18, 18, 18, 17, 17, 16, 16, 15, 14, 14, 13, 13, 12, 12, 11, 10, 9, 9, 8,
> + 8, 7, 6, 5, 4, 4, 3, 3, 2, 2 },
> + { 19, 19, 18, 18, 17, 17, 16, 15, 15, 14, 14, 13, 13, 12, 11, 11, 10, 9,
> + 9, 8, 8, 7, 6, 5, 4, 4, 3, 3, 2 },
> + { 19, 19, 19, 18, 17, 17, 17, 16, 15, 15, 14, 13, 13, 12, 12, 11, 10, 9,
> + 9, 8, 8, 7, 6, 5, 5, 4, 3, 3, 2 },
> + { 21, 20, 20, 19, 18, 18, 17, 16, 16, 15, 14, 14, 13, 12, 12, 11, 10, 10,
> + 9, 9, 8, 7, 7, 6, 5, 5, 4, 4, 3 },
> + { 22, 21, 21, 20, 19, 19, 18, 17, 17, 16, 15, 15, 15, 14, 13, 13, 12, 11,
> + 11, 11, 10, 9, 9, 8, 7, 7, 6, 6, 5 } };
> +
> +#define PARAM_TABLE(_minmax, _bpc, _row, _col, _is_420) do { \
> + if (bpc == (_bpc)) { \
> + if (_is_420) \
> + return
> rc_range_##_minmax##qp420_##_bpc##bpc[_row][_col]; \
> + else \
> + return
> rc_range_##_minmax##qp444_##_bpc##bpc[_row][_col]; \
> + } \
> } while (0)
>
> -u8 intel_lookup_range_min_qp(int bpc, int buf_i, int bpp_i)
> +u8 intel_lookup_range_min_qp(int bpc, int buf_i, int bpp_i, bool
> +is_420)
> {
> - PARAM_TABLE(min, 8, buf_i, bpp_i);
> - PARAM_TABLE(min, 10, buf_i, bpp_i);
> - PARAM_TABLE(min, 12, buf_i, bpp_i);
> + PARAM_TABLE(min, 8, buf_i, bpp_i, is_420);
> + PARAM_TABLE(min, 10, buf_i, bpp_i, is_420);
> + PARAM_TABLE(min, 12, buf_i, bpp_i, is_420);
>
> MISSING_CASE(bpc);
> return 0;
> }
>
> -u8 intel_lookup_range_max_qp(int bpc, int buf_i, int bpp_i)
> +u8 intel_lookup_range_max_qp(int bpc, int buf_i, int bpp_i, bool
> +is_420)
> {
> - PARAM_TABLE(max, 8, buf_i, bpp_i);
> - PARAM_TABLE(max, 10, buf_i, bpp_i);
> - PARAM_TABLE(max, 12, buf_i, bpp_i);
> + PARAM_TABLE(max, 8, buf_i, bpp_i, is_420);
> + PARAM_TABLE(max, 10, buf_i, bpp_i, is_420);
> + PARAM_TABLE(max, 12, buf_i, bpp_i, is_420);
>
> MISSING_CASE(bpc);
> return 0;
> diff --git a/drivers/gpu/drm/i915/display/intel_qp_tables.h
> b/drivers/gpu/drm/i915/display/intel_qp_tables.h
> index 9fb3c36bd7c6..a9ff9ca29938 100644
> --- a/drivers/gpu/drm/i915/display/intel_qp_tables.h
> +++ b/drivers/gpu/drm/i915/display/intel_qp_tables.h
> @@ -8,7 +8,7 @@
>
> #include <linux/types.h>
>
> -u8 intel_lookup_range_min_qp(int bpc, int buf_i, int bpp_i);
> -u8 intel_lookup_range_max_qp(int bpc, int buf_i, int bpp_i);
> +u8 intel_lookup_range_min_qp(int bpc, int buf_i, int bpp_i, bool
> +is_420);
> +u8 intel_lookup_range_max_qp(int bpc, int buf_i, int bpp_i, bool
> +is_420);
>
> #endif
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
> b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index 207b2a648d32..ed16f63d6355 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -422,9 +422,9 @@ calculate_rc_params(struct rc_parameters *rc,
> for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {
> /* Read range_minqp and range_max_qp from qp tables */
> rc->rc_range_params[buf_i].range_min_qp =
> - intel_lookup_range_min_qp(bpc, buf_i, bpp_i);
> + intel_lookup_range_min_qp(bpc, buf_i, bpp_i, vdsc_cfg-
> >native_420);
> rc->rc_range_params[buf_i].range_max_qp =
> - intel_lookup_range_max_qp(bpc, buf_i, bpp_i);
> + intel_lookup_range_max_qp(bpc, buf_i, bpp_i, vdsc_cfg-
> >native_420);
>
> /* Calculate range_bgp_offset */
> if (bpp <= 6) {
> --
> 2.25.1
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