[PATCH] drm/bridge: nwl-dsi: fix packet read ISR handling

[Neil Armstrong]

Hi,

On 18/03/2023 23:36, Kevin Groeneveld wrote:
> In some cases the NWL_DSI_RX_PKT_PAYLOAD_DATA_RCVD interrupt flag is not
> set along with NWL_DSI_RX_PKT_HDR_RCVD when the initial interrupt fires.
> Since the NWL_DSI_RX_PKT_PAYLOAD_DATA_RCVD_MASK was not set then the ISR
> does not fire again when NWL_DSI_RX_PKT_PAYLOAD_DATA_RCVD is finally set
> and the read times out.
> 
> Also the read packet handling checks for NWL_DSI_DPHY_DIRECTION which is
> not always set when the ISR for reading the payload runs. Instead it seems
> better to check xfer->direction is DSI_PACKET_RECEIVE (more similar to the
> send packet case).
> 
> The above two changes were required to perform a successful DCS read from
> a display with a Chipone ICNL9707 driver IC.
> 
> Signed-off-by: Kevin Groeneveld <kgroeneveld at lenbrook.com>


Thanks for the patch, can you provide a Fixes tag ?

Neil

> ---
>   drivers/gpu/drm/bridge/nwl-dsi.c | 3 ++-
>   1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/bridge/nwl-dsi.c b/drivers/gpu/drm/bridge/nwl-dsi.c
> index 6dc2a4e191d7..241568a17f60 100644
> --- a/drivers/gpu/drm/bridge/nwl-dsi.c
> +++ b/drivers/gpu/drm/bridge/nwl-dsi.c
> @@ -334,6 +334,7 @@ static int nwl_dsi_init_interrupts(struct nwl_dsi *dsi)
>   {
>   	u32 irq_enable = ~(u32)(NWL_DSI_TX_PKT_DONE_MASK |
>   				NWL_DSI_RX_PKT_HDR_RCVD_MASK |
> +				NWL_DSI_RX_PKT_PAYLOAD_DATA_RCVD_MASK |
>   				NWL_DSI_TX_FIFO_OVFLW_MASK |
>   				NWL_DSI_HS_TX_TIMEOUT_MASK);
>   
> @@ -489,7 +490,7 @@ static void nwl_dsi_finish_transmission(struct nwl_dsi *dsi, u32 status)
>   	    status & NWL_DSI_TX_PKT_DONE) {
>   		xfer->status = xfer->tx_len;
>   		end_packet = true;
> -	} else if (status & NWL_DSI_DPHY_DIRECTION &&
> +	} else if (xfer->direction == DSI_PACKET_RECEIVE &&
>   		   ((status & (NWL_DSI_RX_PKT_HDR_RCVD |
>   			       NWL_DSI_RX_PKT_PAYLOAD_DATA_RCVD)))) {
>   		end_packet = nwl_dsi_read_packet(dsi, status);