[PATCH 2/2] drm/exynos: Implement support for DSI clock and data lane polarity swap

[Jagan Teki]

On Wed, Mar 29, 2023 at 8:12 PM Fabio Estevam <festevam at gmail.com> wrote:
>
> From: Marek Vasut <marex at denx.de>
>
> Implement support for DSI clock and data lane DN/DP polarity swap by
> means of decoding 'lane-polarities' DT property. The controller does
> support DN/DP swap of clock lane and all data lanes, the controller
> does not support polarity swap of individual data lane bundles, add
> a check which verifies all data lanes have the same polarity.
>
> This has been validated on an imx8mm board that actually has the MIPI DSI
> clock lanes inverted.
>
> Signed-off-by: Marek Vasut <marex at denx.de>
> Signed-off-by: Fabio Estevam <festevam at denx.de>
> ---

Prefix would be "drm: bridge: samsung-dsim: "

Otherwise look good to me, I will give a test and update.

Reviewed-by: Jagan Teki <jagan at amarulasolutions.com>