[PATCH 1/2] dt-bindings: display: exynos: dsim: Add 'lane-polarities'

[Jagan Teki]

On Thu, Mar 30, 2023 at 1:08 PM Krzysztof Kozlowski
<krzysztof.kozlowski at linaro.org> wrote:
>
> On 29/03/2023 16:41, Fabio Estevam wrote:
> > From: Fabio Estevam <festevam at denx.de>
> >
> > The Samsung DSIM IP block allows the inversion of the clock and
> > data lanes.
> >
> > Add an optional property called 'lane-polarities' that describes the
> > polarities of the MIPI DSI clock and data lanes.
> >
> > This is property is useful for properly describing the hardware
> > when the board designer decided to switch the polarities of the MIPI DSI
> > clock and/or data lanes.
> >
> > Signed-off-by: Fabio Estevam <festevam at denx.de>
> > ---
> >  .../devicetree/bindings/display/exynos/exynos_dsim.txt      | 6 ++++++
> >  1 file changed, 6 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt b/Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt
> > index 2a5f0889ec32..65ed8ef7aed7 100644
> > --- a/Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt
> > +++ b/Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt
> > @@ -29,6 +29,12 @@ Required properties:
> >
> >  Optional properties:
> >    - power-domains: a phandle to DSIM power domain node
> > +  - lane-polarities: Array that describes the polarities of the clock and data lanes.
> > +    1: inverted polarity
> > +    0: normal polarity
> > +    The first entry corresponds to the clock lanes. Subsequent entries correspond to the data lanes.
> > +    Example of a 4-lane system with only the clock lanes inverted:
> > +    lane-polarities = <1 0 0 0 0>;
>
> First, please convert to DT schema.

I have a previous iteration of this conversion. Can I resend it on top
of drm-misc-next?
https://lore.kernel.org/all/20210704090230.26489-9-jagan@amarulasolutions.com/

Jagan.